• International Journal of Aeronautical and Space Sciences
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• v.17 no.2
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• pp.232-239
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• 2016

Recently, in order to increase the efficiency and mission success rate of UAVs (Unmanned Aerial Vehicles), the necessity for formation flights is increased. In general, GPS (Global Positioning System) is used to obtain the relative position of leader with respect to follower in formation flight. However, it can't be utilized in environment where GPS jamming may occur or communication is impossible. Therefore, in this study, monocular vision is used for measuring relative position. General PC-based vision processing systems has larger size than embedded systems and is hard to install on small vehicles. Thus FPGA-based processing board is used to make our system small and compact. The processing system is divided into two blocks, PL(Programmable Logic) and PS(Processing system). PL is consisted of many parallel logic arrays and it can handle large amount of data fast, and it is designed in hardware-wise. PS is consisted of conventional processing unit like ARM processor in hardware-wise and sequential processing algorithm is installed on it. Consequentially HW/SW co-designed FPGA system is used for processing input images and measuring a relative 3D position of the leader, and this system showed RMSE accuracy of 0.42 cm ~ 0.51 cm.

• Transactions of the Korean hydrogen and new energy society
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• v.15 no.4
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• pp.274-282
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• 2004

This study focused on the development of high performance catalyst for autothermal reforming (ATR) of gasoline to produce hydrogen. The ATR was carried out over MgO/Al2O3 supported metal catalysts prepared under various experimental conditions. The catalysts before and after reaction were characterized by N2-physisorption, CO-chemisorption, SEM and XRD. The performance of supported multi-metal catalysts were better than that of supported mono-metal catalysts. Especially, it was observed that the conversion of iso-octane over prepared Ni/Fe/MgO/Al2O3 catalyst was 99.9 % comparable with commercial catalyst (ICI) and the selectivity of hydrogen over the prepared catalyst was 65% higher than ICI catalyst. Furthermore, it was identified that the sulfur tolerance of prepared catalyst was much better than ICI catalyst based on the ATR reaction of iso-octane containing sulfur of 100 ppm. Therefore, Ni/Fe/MgO/Al2O3 catalyst can be applied for a fuel reformer, hydrogen station and on-board reformer in furl cell powered vehicles.

• Smart Structures and Systems
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• v.16 no.3
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• pp.383-399
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• 2015

Today, as railways increase their capacity and speeds, it is more important than ever to be completely aware of the state of vehicles fleet's condition to ensure the highest quality and safety standards, as well as being able to maintain the costs as low as possible. Operation of a modern, dynamic and efficient railway demands a real time, accurate and reliable evaluation of the infrastructure assets, including signal networks and diagnostic systems able to acquire functional parameters. In the conventional system, measurement data are reliably collected using coaxial wires for communication between sensors and the repository. As sensors grow in size, the cost of the monitoring system can grow. Recently, auto-powered wireless sensor has been considered as an alternative tool for economical and accurate realization of structural health monitoring system, being provided by the following essential features: on-board micro-processor, sensing capability, wireless communication, auto-powered battery, and low cost. In this work, an original harvester device is designed to supply wireless sensor system battery using train bogie energy. Piezoelectric materials have in here considered due to their established ability to directly convert applied strain energy into usable electric energy and their relatively simple modelling into an integrated system. The mechanical and electrical properties of the system are studied according to the project specifications. The numerical formulation is implemented with in-house code using commercial software tool and then experimentally validated through a proof of concept setup using an excitation signal by a real application scenario.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.70-76
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• 2015

This paper introduces an FPGA self-test architecture reusing FPGA boundary scan chain as self-test circuits. An FPGA boundary scan cell is two or three times bigger than a normal boundary scan cell because it is used for configuring the function of input/output pins functions as well as testing and debugging. Accordingly, we analyze the architecture of an FPGA boundary scan cell in detail and design a set of built-in self-test (BIST) circuits in which FPGA boundary scan chain and a small amount of FPGA logic elements. By reusing FPGA boundary scan chain for self-test, we can reduce area overhead and perform a processor based on-board FPGA testing/monitoring. Experimental results show the area overhead comparison and simulation results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.257-260
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm“Rijndael”. To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation the round transformation block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.33-43
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into a round transformation block, resulting that two consecutive round functions are simultaneously operated. For area-efficient and low-power implementation, the round transformation block is designed to share the hardware resources for encryption and decryption. An efficient on-the-fly key scheduler is devised to supports the three master-key lengths of 128-b/192-b/256-b, and it generates round keys in the first sub-pipeline stage of each round processing. The Verilog-HDL model of the cryptoprocessor was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}m$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• The Journal of the Acoustical Society of Korea
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• v.20 no.1
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• pp.56-61
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• 2001

This paper presents the real-time implementation of an AMR (Adaptive Multi Rate) vocoder which is included in the asynchronous International Mobile Telecommunication (IMT)-2000 mobile ASIC. The implemented AMR vocoder is a multi-rate coder with 8 modes operating at bit rates from 12.2kbps down to 4.75kbps. Not only the encoder and the decoder as basic functions of the vocoder are implemented, but VAD (Voice Activity Detection), SCR (Source Controlled Rate) operation and frame structuring blocks for the system interface are also implemented in this vocoder. The DSP for AMR vocoder implementation is a 16bit fixed-point DSP which is based on the TeakLite core and consists of memory block, serial interface block, register files for the parallel interface with CPU, and interrupt control logic. Through the implementation, we reduce the maximum operating complexity to 24MIPS by efficiently managing the memory structure. The AMR vocoder is verified throughout all the test vectors provided by 3GPP, and stable operation in the real-time testing board is also proved.

• Journal of the Korean Solar Energy Society
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• v.39 no.6
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• pp.55-65
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• 2019

With the rapid development of the national industry, the importance of electrical safety was recognized because of a lot of new electrical equipment are installing and the electrical accidents have been occurring annually. Today, the electrical equipments is inspect by using the portable Infrared thermal imaging camera. but the most negative element of using the camera is inspected for only state of heating, the reliable diagnosis is depended with inspector's knowledge, and real-time monitoring is impossible. This paper present the infrared thermal imaging safety diagnosis system. This system is able to monitor in real time, predict the state of fault, and diagnose the state with analysis of thermal and power data. The system consists of a main processor, an infrared camera module, the power data acquisition board, and a server. The diagnostic algorithm is based on a mathematical model designed by analyzing the Pearson's Correlation Coefficient between temperature and power data. To test the prediction algorithm, the simulations were performed by damaging the terminals or cables on the switchboard to generate a large amount of heat. Utilizing these simulations, the developed prediction algorithm was verified.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.7
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• pp.737-747
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• 2013

A 3-D surveillance radar is a pulsed-doppler radar to provide various target information, such as range, doppler and angle by performing TWS. This paper introduces HW/SW architecture of radar signal processing board to process in real-time using high-speed multiple DSP(Digital Signal Processor) based on COTS. Moreover, we introduced a implemented algorithm consisted of clutter map creation/renewal, FIR(Finite Impulse Response) filter for rejection of zero velocity components, doppler filter, hybrid CFAR and finally presented computational burden of each algorithm by performing operational test using a beacon.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.12
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• pp.1008-1012
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• 2009

Obfuscation is known as one of the most effective methods to protect software against malicious reverse engineering transforming the software into more complicated one with still preserving the original semantic. However, obfuscating a program can increase both code size of the program and execution time compared to the original program. In mobile devices, the increases of code size and execution time incur the waste of resources including the increase of power consumption. This paper has analyzed the effectiveness of some high-level obfuscation algorithms as well as their power consumption with implementing them under an embedded board equipped with ARM processor. The analysis results show that there is (are) an efficient obfuscation method(s) in terms of execution time or power consumption according to characteristics of a given program.