• Proceedings of the KIEE Conference
• /
• 2006.04a
• /
• pp.255-257
• /
• 2006

This paper proposed a platform which includes both Network processor and DSP for flexible IED. The Network processor is one of the Intel's IXP4XX Product Line family and the DSP is one of the TI's C6000 family. An embedded Linux is ported in Network processor so that a DSP program can be downloaded to Network processor through ethernet and then downloaded to DSP. Using this method, various algorithms according to IED can be applied to the Network processor board. Maximum ten ADCs can be connected because there is a CPLD between DSP and ADC. That is, the network processor board which can measure maximum 40 channels is implemented. In DSP program, thread and double buffering methods are used not to miss voltage samples. The Network processor board is verified using a method that eight channel voltage signals converted to digital are transmitted to server through both DSP and IXP425.

• Proceedings of the KIEE Conference
• /
• 2005.05a
• /
• pp.194-196
• /
• 2005

The command processor in satellite handles the capability of the process of command transmitted from ground station and deliver the processed data to on board computer in satellite. The command processor is consisted of redundant box to increase the reliability and availability of the capability. At each command processor, the processing time of each command processor is different, so the mismatch of processing time makes it difficult to timely synchronize the reception to on board computer and even will be became worse under the command processor's fault. To minimize the tine loss induced by the command processor's fault on board computer must analyze the time distribution of command propagation. This paper presents the logic of minimizing the delay error of command propagation the logic of analyzing the output of command processor.

• Journal of the Korea Institute of Military Science and Technology
• /
• v.8 no.2 s.21
• /
• pp.30-37
• /
• 2005

In this paper, we propose how to design a fire control system main control board for individual combat weapons using a small and low power processor. To design an electric board of small weapon systems, Size and power consumption are very important factors. We solved the problem using selection of an adaptive processor, introduction of MicroChipPackaging method, and separate design of a main board Also we applied these methods to make the fire control system for small arms.

• Proceedings of the KIEE Conference
• /
• 2003.11c
• /
• pp.1014-1017
• /
• 2003

In this paper, after the crypto acceleration board of the server-termination type is designed, we implement the Elliptic Curve Digital Signature Algorithm on the board that serves data integrity and user authentication. For implementing ECDSA, we use crypto co-processor, MPC180, to reduce the computation burden of main Processor (MPC860) on the board. By using crypto co-processor, the computation efficiency in case prime field is improved more between 90 and 100 times than the software library and between 20 and 90 times in case binary field. Our result is expect to apply for SSL acceleration board.

• 제어로봇시스템학회:학술대회논문집
• /
• 1993.10a
• /
• pp.685-691
• /
• 1993

This paper introduces a PC-based image data processing unit that is composed of preprocessor board and main processor board; The preprocessor contains Inmos A110 processor and efficient H/W architecture for fast mask/logic operations at the speed of video signal rate. It is controlled by the main processor which communicates with the host PC. The main processor board contains TI TMS320C31 digital signal processor, and can access the frame memory of the processor for extra S/W tasks. We test 3*3, 5*5 masks and logic operations on 386/486/DSP and compare the result with that of the proposed unit. The result shows ours are extremely faster than conventional CPU based approach, that is, over several hundred times faster than even DSP.

• Journal of Institute of Control, Robotics and Systems
• /
• v.3 no.6
• /
• pp.626-631
• /
• 1997

This paper represents the design of a real-time image preprocessing system. The preprocessing system performs hardware-wise mask operations and thresholding operations at the speed of camera output single rate. The preprocessing system consists of the preprocessing board and the main processing board. The preprocessing board includes preprocessing unit that includes a $5\times5$ mask processor and LUT, and can perform mask and threshold operations in real-time. To achieve high-resolution image input data($20485\timesn$), the preprocessing board has a linescan camera interface. The main processing board includes the image processor unit and main processor unit. The image processor unit is equipped with TI's TMS320C32 DSP and can perform image processing algorithms at high speed. The main processor unit controls the operation of total system. The proposed system is faster than the conventional CPU based system.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.17 no.4
• /
• pp.633-640
• /
• 2022

As service robots are applied to various fields, interest in an image processing processor that can perform an image processing algorithm quickly and accurately suitable for each task is increasing. This paper introduces an image processing processor design method applicable to robots. The proposed processor consists of an AGX board, FPGA board, LiDAR-Vision board, and Backplane board. It enables the operation of CPU, GPU, and FPGA. The proposed method is verified through simulation experiments.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.33B no.2
• /
• pp.149-158
• /
• 1996

In this paper we describe designing and implementing a digital neural chip and a parallel neural machine for simulating large scale neural netsorks. The chip is a single-chip multiprocessor which has four digiral neural processors (DNP-II) of the same architecture. Each DNP-II has program memory and data memory, and the chip operates in MIMD (multi-instruction, multi-data) parallel processor. The DNP-II has the instruction set tailored to neural computation. Which can be sed to effectively simulate various neural network models including on-chip learning. The DNP-II facilitates four-way data-driven communication supporting the extensibility of parallel systems. The parallel neural machine consists of a host computer, processor boards, a buffer board and an interface board. Each processor board consists of 8*8 array of DNP-II(equivalently 2*2 neural chips). Each processor board acn be built including linear array, 2-D mesh and 2-D torus. This flexibility supports efficiency of mapping from neural network models into parallel strucgure. The neural system accomplishes the performance of maximum 40 GCPS(giga connection per second) with 16 processor boards.

• 전자공학회논문지 IE
• /
• v.47 no.3
• /
• pp.1-6
• /
• 2010

In this paper, it is designed a processor using embedded system so that moving picture can be expressed on LED electric sign board which has been expressed a simple message only like as a character or graphic. It has been fabricated a moving picture LED electric sign board which is composed to a video processor and LED display panel, in order to be able to express a digital moving picture of 24 bits that is transmitted from embedded system. It includes gamma adjustment, brightness, color contrast control, a schedule function, expression image conversion by the Internet and memory device. Also, an application program based Windows CE is designed so that a character, graphic, and moving picture can be expressed on a small LED electric sign board.

• Journal of Advanced Marine Engineering and Technology
• /
• v.35 no.2
• /
• pp.288-294
• /
• 2011

In this paper, the FPGA-based SoC board (Xilinx Virtex-4 ML401 EVM) is adopted to control electrical power inverter system. For marine application, its performance is shown on PC-based system for monitoring electrical characteristics of a power inverter using by the NMEA 2000 protocol. This power inverter system is achieved in Real-Time monitoring and control by dual micro-processor operation on embedded FPGA-based SoC board. One micro processor is for control (Control processor) electrical power inverter using by PWM signal. And the other microprocessor (Communication processor) is for communication with PC-based monitoring system. The two-processor is communicating each other using by dual-port ram (DPRAM). PC-based system user can control and monitor information of the electrical power inverter via NMEA 2000 based communication processor. Control and monitoring information includes the inverter status and configuration. SoC board converts this information to Parameter Group Numbers (PGNs) in the NMEA 2000 protocol. This system can be applied to marine power electronics for distributed power generation, transmission or regulation systems on the ship.