• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8A
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• pp.1134-1143
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• 2000

We propose a scheduling algorithm, Bandwidth Allocation Scheme (BAS), that guarantees bounded delay in a switching node. It is based on the notion of the GPS (Generalized Processor Sharing) mechanism, which has clarified the concept of fair queueing with a fluid-flow hypothesis of traffic modeling. The main objective of this paper is to determine the session-level weights that define the GPS sewer. The way of introducing and derivation of the so-called system equation' implies the approach we take. With multiple classes of traffic, we define a set of service curves:one for each class. Constrained to the required profiles of individual service curves for delay satisfaction, the sets of weights are determined as a function of both the delay requirements and the traffic parameters. The schedulability test conditions, which are necessary to implement the call admission control, are also derived to ensure the proposed bandwidth allocation scheme' be able to support delay guarantees for all accepted classes of traffic. It is noticeable that the values of weights are tunable rather than fixed in accordance with the varying system status. This feature of adaptability is beneficial towards the enhanced efficiency of bandwidth sharing.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.4
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• pp.383-393
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• 2000

In shared memory multiprocessor systems, false sharing occurs when several independent data objects, not shared but accessed by different processors, are allocated to the same coherency unit of memory. False sharing is one of the major factors that may degrade the performance of memory coherency protocols. This paper presents a new shared memory allocation scheme to reduce false sharing of parallel applications where master processor controls allocation of all the shared objects. Our scheme allocates the objects to temporary address space for the moment, and actually places each object in the address space of processor that first accesses the object later. Its goal is to allocate independent objects that may have different access patterns to different pages. We use execution-driven simulation of real parallel applications to evaluate the effectiveness of our scheme. Experimental results show that by using our scheme a considerable amount of false sharing faults can be reduced with low overhead.

• The KIPS Transactions:PartA
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• v.8A no.3
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• pp.245-252
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• 2001

Multicomputer systems achieve high performance by utilizing a number of computing nodes. Multidimensional meshes have become popular as multicomputer architectures due to their simplicity and efficiency. In this paper we propose an efficient processor allocation scheme for 3D torus based on first-fit approach. The scheme minimizes the allocation time by effectively manipulating the 3D information an 2D information using CST (Coverage Status Table). Comprehensive computer simulation reveals that the allocation time of the proposed scheme is always smaller than the earlier scheme based on best-fit approach, while allowing comparable processor utilization. The difference gets more significant as the input load increases. To investigate the performance of the proposed scheme with different scheduling environment, non-FCFs scheduling policy along with the typical FCFS policy is also studied.

• Journal of Internet Computing and Services
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• v.8 no.1
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• pp.133-142
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• 2007

Large database processing is one of the most important technique in the information society, Since most large database is regionally distributed, the distributed database processing has been brought into relief. Communications and data compressions are the basic technologies for large database processing. In order to maximize those technologies, the execution time for the task, the size of data, and communication time between processors should be considered. In this paper, the dataflow scheme and vertically layered allocation algorithm have been used to optimize the distributed large database processing. The basic concept of this method is rearrangement of processes considering the communication time between processors. The paper also introduces measurement model of the execution time, the size of output data, and the communication time in order to implement the proposed scheme.

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1082-1091
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• 2000

In Distributed Shared Memory systems, false sharing occurs when two different data items, not shared but accessed by two different processors, are allocated to a single block and is an important factor in degrading system performance. The paper first analyzes shared memory allocation and reference patterns in parallel applications that allocate memory for shared data objects using a dynamic memory allocator. The shared objects are sequentially allocated and generally show different reference patterns. If the objects with the same size are requested successively as many times as the number of processors, each object is referenced by only a particular processor. If the objects with the same size are requested successively much more than the number of processors, two or more successive objects are referenced by only particular processors. On the basis of these analyses, we propose a memory allocation scheme which allocates each object requested by different processors to different pages and evaluate the existing memory allocation techniques for reducing false sharing faults. Our allocation scheme reduces a considerable amount of false sharing faults for some applications with a little additional memory space.

• The KIPS Transactions:PartA
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• v.12A no.2 s.92
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• pp.117-126
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• 2005

This paper presents an adaptive processor allocation strategy to reduce fragmentation in a large multi-user multicomputer system. A small number of jobs with unexpectedly large submesh allocation requirements may significantly increase the queuing delay of the rest of jobs. Under such circumstances, our strategy further tries to allocate L-shaped submeshes instead of signaling the allocation failure unlike other strategies. We have developed the efficient algorithm to find the allocatable L-shaped submeshes. Thus, our strategy reduces the mean response time by minimizing the queuing delay, even though jobs are scheduled in an FCFS to preserve fairness. The simulations show that our strategy performs more efficiently than other strategies in terms of the job response time and the system utilization.

• The Transactions of the Korea Information Processing Society
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• v.6 no.2
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• pp.497-511
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• 1999

Recently, many parallel processing technologies were developed, ILP(Instruction level Parallelism) processor's performance have been growed very rapidly. especially, EPIC(Explicitly Parallel Instruction computing) architectures attempt to enhance the performance in the predicated execution and speculative execution with the hardware. In this paper to improve the code scheduling possibility by applying to the characteristics of EPIC architectures, a new register allocation algorithm is proposed. And we proves that proposed register allocation algorithm is more efficient scheme than the conventional scheme when predicated execution is applied to our scheme by experiments. In experimental results, it shows much more performance enhancement, about 19% in proposed scheme than the conventional scheme. So, our scheme is verified that it is an effective register allocation method.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.6
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• pp.9-21
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• 2003

In this paper, we propose a new submesh allocation scheme which improves the performance of multicomputer systems. The key idea of this allocation scheme is to reduce waiting time of task by minimizing the submesh search time and the submesh a]location delay caused by external fragmentation. This scheme reduces the submesh search time by classifying independent free submeshes according to their types (square, horizontal rectangle, vertical rectangle) and searching a best-fit submesh from the classified free submesh list. If a submesh allocation delay occurs due to external fragmentation, the proposed scheme relocates tasks, executing In allocated submeshes, to another free submeshes and compacts processor fragmentation. This results in reducing the submesh allocation delay. Through simulation, we show that it is more effective to reduce the submesh allocation delay due to external fragmentation than reducing the submesh search time with respect to the waiting time of task. We also show that the proposed strategy improves the performance compared to previous strategies.

• The KIPS Transactions:PartA
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• v.18A no.6
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• pp.265-270
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• 2011

Even though 32-bit ISA based microprocessors are widely used more and more, 16-bit ISA based processors are still being frequently employed for embedded systems. Intel 8086, 80286, Motorola 68000, and ADChips AE32000 are the representatives of the 16-bit ISA based processors. However, due to less expressiveness of the 16-bit ISA from its narrow bit width, we need to execute more 16-bit instructions for the same implementation compared to 32-bit instructions. Because the number of executed instructions is a very important factor in performance, we have to resolve the problem by improving the expressiveness of the 16-bit ISA. In this paper, we propose a new pair register allocation algorithm to enhance an original graph-coloring based register allocation algorithm. Also, we explain about both the performance result and further research directions.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.2
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• pp.96-102
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• 2014

The embedded processor market has grown rapidly and consistently with the appearance of mobile devices. In an embedded system, the power consumption and execution time are important factors affecting the performance. The system performance is determined by both hardware and software. Although the hardware architecture is high-end, the software runs slowly due to the low quality of codes. This study compared the performance of two major compilers, LLVM and GCC on a32-bit EISC embedded processor. The dynamic instructions and static code sizes were evaluated from these compilers with the EEMBC benchmarks.LLVM generally performed better in the ALU intensive benchmarks, whereas GCC produced a better register allocation and jump optimization. The dynamic instruction count and static code of GCCwere on average 8% and 7% lower than those of LLVM, respectively.