• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.430-433
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• 1999

Woo[8]proposed dual-token based fault-tolerant scheduling algorithm in multiprocessor environment for resolving the problem of old systems that have a central dispatcher processor. However, this algorithm does not present token allocation algorithm in detail when central dispatcher processor has failed. In this paper, we propose a fault detection algorithm and processor selection algorithm for token allocation when central dispatcher processor has failed.

• 산업경영시스템학회지
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• 제17권32호
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• pp.145-154
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• 1994

In this paper, monitoring processor in a circuit switched network is considered. Monitoring processor monitors communication links, and offers a grade of service in each link to controller. Such an information is useful for an effective maintenance of system. Two links with nonsymmetric system Parameters are considered. each link is assumed independent M/M/1/1 type. The Markov process is introduced to compute busy and idle portions of monitoring processor and monitored rate of each link. Inter-idle times and inter-monitoring times of monitoring processor between two links are respectively computed. A recursive formula is introduced to make computational procedure rigorous.

• 전자공학회논문지B
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• 제31B권12호
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• pp.1-10
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• 1994

In this paper, we propose a processor allocation algorithm using the PGG(Packed Gray code Group) for the MIMD hypercube. The number of k-D subcubes in an n-cube is C(n.k) en-k. When the PGG is employed in the processor allocation, C(n, k) PGG's are required to recognize all the k-D subcubes in an n-cube. from the simulation we find that the capability of processor allocation using only 40% of C(n, k) PGG's is about the same as that of the allocation using all the PGG's.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.74-76
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• 2007

This paper presents the hardware design of a 32bit floating point based processor. The processor can perform nonlinear functions such as sinusoidal functions, exponential functions, and other nonlinear functions. Using the Taylor series and the Newton - Raphson method, nonlinear functions are approximated. The processor is actually embedded on an FPGA chip and tested. The numerical accuracy of the functions is compared with those computed by the MATLAB.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(1)
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• pp.5-8
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• 2002

In this paper, we are designed and verified a FFT/IFFT processor that is possible from the wireless LAN environment which is adopted international standard of the IEEE802.11a. The proposed architecture of the FFT/IFFT has Radix-2 64point SDF(single-path delay feedback) Pipeline technique and DIF(Decimation in Frequenct) structure. The FFT/IFFT processor has each 8 bit complex input-output and 6 bit Twiddle factor. we used Max-PlusII for simulation and can see that processor is properly operated

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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• pp.201-204
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• 1987

To improve the reliability of boiler controller of a power plant, FTCS(Fault Tolerant Control System) is proposed. We studied to implement a Multi-processor scheme for FTCS. This paper presents the total system to experiment the performance of FTCS and the Multi-processor scheme implemented.

• 한국항해학회지
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• 제14권4호
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• pp.31-39
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• 1990

A systematic methodology for efficient implementation of processor arrays from regular iterative algorithms is proposed. One of the modern parallel processing array architectures is the Systolic arrays and we use it for processor arrays on this paper. On designing the systolic arrays, there are plenty of mapping functions which satisfy necessary conditions for its implementation to the time-space domain. In this paper, we sue a few conditions to reduce the total number of computable mapping functions efficiently. As a results of applying this methodology, efficient designs of systolic arrays could be done with considerable saving on design time and efforts.

• 융합신호처리학회 학술대회논문집
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• 한국신호처리시스템학회 2000년도 하계종합학술대회논문집
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• pp.341-344
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• 2000

The 0-1 knapsack processor performing dynamic programming is designed and implemented on a programmable logic device. Three types of a processor, each with different behavioral models, are presented, and the operation of a processor of each type is verified with an instance of the 0-1 knapsack problem.

• 한국통신학회논문지
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• 제19권10호
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• pp.2043-2052
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• 1994

본 논문에서는 근접한 Processing Element(PE)들간의 통신 부담을 경감시켜 영상신호를 실시간 처리할 수 있는 새로운 병렬처리 방식 ASIC 구조를 설계한다. 하나의 Sliding Memory Plane (SliM) Image Processor chip을 병렬처리 방식을 사용 $3\times3$ PE를 격자 형태로 연결한다. 제안하는 Image Processor를 구현할 수 있다. Sliding 개념은 별도의 보조 프로세서나 DMA를 사용치 않고 또한 PE들을 interupt 걸지 않고 모든 화소가 이웃 PE로 이동됨을 의미한다. 따라서 근접 통신과 계산이 동시에 일어나 기존의 격자 연결 병렬 컴퓨터의 결정적 단점인 근접 통신 부담을 경감시킬 수 있다. 또한 하나의 PE에 두 개의 입출력용 레지스터 plane을 사용, buffer를 제공하여 입출력 부담을 감소시킨다. SliM Image Processor에서는 단지 4개의 통신 link만으로 8가지 방향의 통신경로를 제공하는 by-passing path에 의해 통신 부담없이 대각선 통신을 수행할 수 있다. 제안하는 유일한 특성들로 인해 영상 신호 처리시 성능을 향상시킬 수 있다. 영상신호 처리를 위한 알고리즘들을 효율적으로 수행키 위한 PE, Image Processor 구조 및 명령어를 설계한다.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2010년도 춘계학술대회 초록집
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• pp.123.2-123.2
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• 2010

Fuel Cell cogeneration system is a promising technology for generating electricity and heat with high efficiency of low pollutant emission. We have been developed 5kW class fuel cell cogeneration system for commercial and residential application. The fuel processor is a crucial part of producing hydrogen from the fossil fuels such as LNG and LPG. The 5kW class high efficiency fuel processor consists of steam reformer, CO shift converter, CO preferential oxidation(PrOx) reactor, burner and heat exchanger. The one-stage CO shift converter process using a metal oxide catalyst was adopted. The efficiency of 5 kW class fuel processor shows 75% based on LHV. In addition, for the purpose of continuous operation with load fluctuations in the commercial system for residential use, load change of fuel processor was tested. Efficiency of 30%, 50%, 70% and 100% load shows 75%, 75%, 73% and 72%(LHV), respectively. Also, during the load change conditions, the product gas composition was stable and the outlet CO concentration was below 5 ppm. The Fuel processor operation was carried out in residential fuel cell cogeneration system with fuel cell stack under dynamic conditions. The 5kW class fuel processor have been evaluated for long-term durability and reliability test including with improvement in optimal operation logic.