• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1999.11b
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• pp.255-260
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• 1999

This paper shows the design of a high throughput 512-point FFT processor. The performance target of the 512-point FFT processor is to achieve data symbol rate required for OFDM systems. The memory requirement of the 512-point FFT processor is minimized by adopting shuffle memory system. The hardware cost of the 512-point in processor is further reduced by using a complex multiplier with a new strength reduction method.

• Electronics and Telecommunications Trends
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• v.35 no.3
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• pp.66-75
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• 2020

As the increasing expectations of a practical AI (Artificial Intelligence) service makes AI algorithms more complicated, an efficient processor to process AI algorithms is required. To meet this requirement, processors optimized for parallel processing, such as GPUs (Graphics Processing Units), have been widely employed. However, the GPU has a generalized structure for various applications, so it is not optimized for the AI algorithm. Therefore, research on the development of AI processors optimized for AI algorithm processing has been actively conducted. This paper briefly introduces an AI processor especially for inference acceleration, developed by the Electronics and Telecommunications Research Institute, South Korea., and other global vendors for mobile and server platforms. However, the GPU has a generalized structure for various applications, so it is not optimized for the AI algorithm. Therefore, research on the development of AI processors optimized for AI algorithm processing has been actively conducted.

• Proceedings of the Korea Multimedia Society Conference
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• 2000.04a
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• pp.117-120
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• 2000

This paper describe VLSL design of crytographic processor which can execute triple DES and DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has 1 unrolled loop structure without pipeline and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation , the key precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O techniques is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is implemented using Altera EPF10K40RC208-4 devices and has peak performance of about 75 Mbps under 20 Mhz ECB DES mode and 25 Mbps uder 20 Mhz triple DES mode.

• Journal of the Korean Operations Research and Management Science Society
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• v.18 no.1
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• pp.45-54
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• 1993

Monitoring processor in a circuit switched network is considered. Monitoring processor monitors communication links offers a grade of service in each link to controller. Such an information is useful for an effective maintenance of system. Two links with asymmetric system parameters and multi-symmetric links are respectively considered. Each links is to be an independent M /M/ 1/ 1/ type. Markov modeling technique is used to represent a model of monitoring processor with FCFS steering protocol. Performance measures considered are ratio of monitored jobs in each link, availability of minitoring processor and throughput of virtual processor in each link. The value of the performance meausres are compared with existing and simulation results.

• Journal of Biomedical Engineering Research
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• v.6 no.2
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• pp.13-14
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• 1985

We have developed a microprogramir!able signal processor for real-time ultrasonic signal processing. Processing speed was increased by the parallelism in horizontal microprogram using 104bits microcode and the Pipelined architecture. Control unit of the signal processor was designed by microprogrammed architec- ture and writable control store (WCS) which was interfaced with host computer, APPLE- ll . This enables the processor to develop and simulate various digital signal processing algorithms. The performance of the processor was evaluated by the Fast Fourier Transform (FFT) program. The execution time to perform 16 bit 1024 points complex FF7, radix-2 DIT algorithm, was about 175 msec with IMHz master Clock. We can use this processor to Bevelop more efficient signal processing algorithms on the biological signal processing.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.438-443
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• 2005

Handy paint rollers with simple or no patterns are generally used to transcribe its design to a wall just after painting. However, the types of the patterns are limited to several conventional ones, so that interior planners' or decorators' demands are gradually tending to getting attractive roller designs. In order to obtain abundant kinds of the roller designs, a new advanced 3D machining method should be established for cylindrical models. In this paper, a post-processor that can generate suitable NC data is proposed for multi-axis NC machine tools with a rotary unit. The 3D machining system with the post-processor is also presented for an attractive interior decorating. The machining system allows us to easily transcribe the relief designs from on a flat model to on a cylindrical model. The effectiveness of the proposed 3D machining system using the post-processor is demonstrated through some machining experiments.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.11 no.3
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• pp.120-126
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• 2001

The simulation system for analyzing the ceramic drying process is developed. This system consists of 3 parts: pre-processor, analyzer, and post-processor. The pre-processor creates 3-dimensional ceramics, makes finite-element models, and prepares analyzers input. The analyzer computes temperature, moisture, residual stress, displacement, etc. during the drying process using the information about finite-element model, material property, and boundary condition provided by the pre-processor. In post-processor, the analyzers results are visualized to help designers evaluation of the drying of the ceramic.

• Journal of the Korea Society of Computer and Information
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• v.4 no.2
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• pp.27-38
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• 1999

This paper proposes a high speed digital neuron processor which uses the residue number system, making the high speed operation possible without carry propagation,. Consisting of the MAC(Multiplier and with Accumulator) operation unit, quotient operation unit and sigmoid function operation unit, the neuron processor is designed through 0.8$\mu$m CMOS fabrication. The result shows that the new implemented neuron processor can run at the speed of 19.2 nSec and the size can be reduced to 1/2 compared to the neuron processor implemented by the real number operation unit.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.927-930
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• 2003

In this paper, a design of processor IP for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability. To handle the various modes of TCP/IP protocol, hardware and software co-design approach is used rather than the conventional state machine based design. To eliminate delay time due to the data transfer and checksum operation, DAM module which can execute the checksum operation on-the-fly along with data transfer operation is adopted. By programming the on-chip code ROM of RISC processor differently. the designed stack processor can support the packet format conversion operations required in the various TCP/IP protocols.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1027-1030
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• 2003

In this paper, we designed GF(2$^{m}$ ) inversion and division processor for Elliptic Curve Cryptographic system. The processor that has 191 by m value designed using Modified Euclid Algorithm. The processor is designed using 0.35 ${\mu}{\textrm}{m}$ CMOS technology and consists of about 14,000 gates and consumes 370 mW. From timing simulation results, it is verified that the processor can operate under 367 Mhz clock frequency due to 2.72 ns critical path delay. Therefore, the designed processor can be applied to Elliptic Curve Cryptographic system.