• Title/Summary/Keyword: Process-In-Memory (PIM)

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Accelerating ORAM with PIM (PIM을 활용한 ORAM 가속화 연구)

  • Suhwan Shin;Hojoon Lee
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.33 no.2
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    • pp.235-242
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    • 2023
  • ORAM(Oblivious RAM) is an algorithm that defends side channel attacks when the user uses an untrusted server or hardware. ORAM defends against leaks of information by hiding data access patterns. However, ORAM is not in practical use because as ORAM reinforces hardware security, it also has a severe disadvantage in processing speed. In this paper, we suggest using newly introduced hardware, PIM (Process In Memory), to accelerate ORAM and use it practically.

Design of In-Memory Computing Adder Using Low-Power 8+T SRAM (저 전력 8+T SRAM을 이용한 인 메모리 컴퓨팅 가산기 설계)

  • Chang-Ki Hong;Jeong-Beom Kim
    • The Journal of the Korea institute of electronic communication sciences
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    • v.18 no.2
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    • pp.291-298
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    • 2023
  • SRAM-based in-memory computing is one of the technologies to solve the bottleneck of von Neumann architecture. In order to achieve SRAM-based in-memory computing, it is essential to design efficient SRAM bit-cell. In this paper, we propose a low-power differential sensing 8+T SRAM bit-cell which reduces power consumption and improves circuit performance. The proposed 8+T SRAM bit-cell is applied to ripple carry adder which performs SRAM read and bitwise operations simultaneously and executes each logic operation in parallel. Compared to the previous work, the designed 8+T SRAM-based ripple carry adder is reduced power consumption by 11.53%, but increased propagation delay time by 6.36%. Also, this adder is reduced power-delay-product (PDP) by 5.90% and increased energy-delay- product (EDP) by 0.08%. The proposed circuit was designed using TSMC 65nm CMOS process, and its feasibility was verified through SPECTRE simulation.

Design of High-Speed Sense Amplifier for In-Memory Computing (인 메모리 컴퓨팅을 위한 고속 감지 증폭기 설계)

  • Na-Hyun Kim;Jeong-Beom Kim
    • The Journal of the Korea institute of electronic communication sciences
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    • v.18 no.5
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    • pp.777-784
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    • 2023
  • A sense amplifier is an essential peripheral circuit for designing a memory and is used to sense a small differential input signal and amplify it into digital signal. In this paper, a high-speed sense amplifier applicable to in-memory computing circuits is proposed. The proposed circuit reduces sense delay time through transistor Mtail that provides an additional discharge path and improves the circuit performance of the sense amplifier by applying m-GDI (: modified Gate Diffusion Input). Compared with previous structure, the sense delay time was reduced by 16.82%, the PDP(: Power Delay Product) by 17.23%, the EDP(: Energy Delay Product) by 31.1%. The proposed circuit was implemented using TSMC's 65nm CMOS process, while its feasibility was verified through SPECTRE simulation in this study.