• Journal of Digital Convergence
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• v.12 no.3
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• pp.227-235
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• 2014

Mobile virtualization is an approach to mobile device management in which two virtual platforms are installed on a single wireless device. A smartphone, a single wireless device, might have one virtual environment for business use and one for personal use. Mobile virtualization might also allow one device to run two different operating systems, allowing the same phone to run both RTOS and Android apps. In this paper, we propose the techniques to virtualize the cores of a multicore, allowing the reassign any number of vCPUs that are exposed to a OS to any subset of the pCPUs. And then we also propose the real-time scheduling method to assigning the vCPUs to the pCPU. Suggested technology in this paper solves problem that increases time of real-time process when interrupt are handled, and is able more to fast processing than previous algorithm.

• The Journal of the Korea Contents Association
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• v.22 no.8
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• pp.81-93
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• 2022

Recently, research on processing a large-capacity graph using GPUs has been conducting. In order to process a large-capacity graph in a GPU with limited memory, the graph must be divided into subgraphs and then processed by scheduling subgraphs. In this paper, we propose an efficient graph algorithm processing scheme in GPU environments with limited memory and performance evaluation. The proposed scheme consists of a graph differential subgraph scheduling method and a graph segmentation method. The bulk graph segmentation method determines how a large-capacity graph can be segmented into subgraphs so that it can be processed efficiently by the GPU. The differential subgraph scheduling method schedule subgraphs processed by GPUs to reduce redundant transmission of the repeatedly used data between HOST-GPUs. It shows the superiority of the proposed scheme by performing various performance evaluations.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.61-61
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• 2000

Since FMS(Flexible Manufacturing System) such as semiconductor production systems have the characteristic that each device has to be commonly used in several stages, it is difficult to find an optimal solution. In this paper, we proposed the new algorithm which can get the optimal ratio of sharing resources. We will implement the proposed algorithm to semiconductor production systems. We introduce the optimal algorithm, which is modeled and analyzed by ExSpect, a petri net based simulation tool. When there exist conflicts of sharing resources, the scheduling method is adopted, which gives a priority to the most preceded process. The suggested algorithm can be used not only in semiconductor production systems but also in various FMS.

• Journal of applied mathematics & informatics
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• v.15 no.1_2
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• pp.511-525
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• 2004

we model communication and computer systems that process interactive and several and several types of background jobs. The scheduling policy in use is to share the processor among all interactive jobs and, at most, one background job of each type at a time according to the process sharing discipline. Background jobs of each type are served on a first-come-first-served basis. Such scheduling policy is called Processor Sharing with Background jobs (PSBJ). In fact, the PSBJ policy is commonly used on many communication and computer systems that allow interactive usage of the systems and process certain jobs in a background mode. In this paper, the stability conditions for the PSBJ policy are given and proved. Since an exact analysis of the policy seems to be very difficult, an approximate analytic model is proposed to obtain the average job sojourn times. The model requires the solution of a set of nonlinear equations, for which an iterative algorithm is given and its convergence is proved. Our results reveal that the model provides excellent estimates of average sojourn times for both interactive and background jobs with a few percent of errors in most of the cases considered.

• Journal of the Society of Naval Architects of Korea
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• v.33 no.4
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• pp.124-132
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• 1996

This paper discusses a scheduling system effective for producing optimum load distribution in ship design process with particular reference to an accommodation design. Through various analysis of the factors influencing the effectiveness of design process control, it was possible to formulate an algorithm of producing an optimum design schedule. Basic manhours far the ship to be planned by multiplying a difficulty level coefficient for the standard manhours for each design activity is preset, and is converted into manhours for the ship to be planned by multiplying a difficulty level coefficient for the ship. A relation matrix of the design activities is employed in representing the network of the activities. The computerized system showed very effective in producing a design schedule of leveled work load on which particular characteristics of a ship to be planned are properly reflected.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.228-234
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• 2006

This paper describes a systematic process which can generate a complete circuit specification efficiently for a given recursive DSP algorithm based on an optimal multiprocessor scheduler. The process is composed of two states: scheduling and circuit synthesis. The scheduling part accepts a fully specified flow graph(FSFG) as an input, and generates an optimal synchronous multiprocessor schedule. Then the circuit synthesis part translates the modified schedule into a complete circuit diagram including a control specification. The circuit diagram can be applied to a silicon compiler for VLSI layout generation. This paper illustrates the whole process with an example of a second order Gray-Market lattice filter.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.29 no.1
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• pp.1-8
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• 2006

This paper proposes a real-time resource allocation algorithm for minimizing the completion time of overall workflow process. The jobs in a workflow process are interrelated through the precedence graph including Sequence, AND, OR and Loop control structure. A resource should be allocated for the processing of each job, and the required processing time of the job can be varied by the resource allocation decision. Each resource has several inherent restrictions such as the functional, geographical, positional and other operational characteristics. The algorithm suggested in this paper selects an effective resource for each job by considering the precedence constraint and the resource characteristics such as processing time and the inherent restrictions. To investigate the performance of the proposed algorithm, several numerical tests are performed for four different workflow graphs including standard, parallel and two series-parallel structures. In the tests, the solutions by the proposed algorithm are compared with random and optimal solutions which are obtained by a random selection rule and a full enumeration method respectively.

• Journal of Korean Institute of Industrial Engineers
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• v.23 no.4
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• pp.645-660
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• 1997

An application of the genetic algorithm(GA) to the loading sequencing problem in port container terminals is presented in this paper. The efficiency of loading operations in port container terminals is highly dependent on the loading sequence of export containers. In order to sequence the loading operation, we hove to determine the route of each container handling equipment (transfer crane or straddle carried in the yard during the loading operation. The route of a container handling equipment is determined in a way of minimizing the total container handling time. An encoding method is developed which keeps intermediate solutions feasible and speeds up the evolution process. We determine the sequence of each individual container which the container handling equipment picks up at each yard-bay as well as the visiting sequence of yard-bays of the equipment during the loading operation. A numerical experiment is carried out to evaluate the performance of the algorithm developed.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.69-72
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• 2001

High-level synthesis generates a structural design that implements the given behavior and satisfies design constraints for area, performance, power consumption, packaging, testing and other criteria. Thus, high-level synthesis generates that register-transfer(RT) level structure from algorithm level description. High-level syntehsis consist of compiling, partitioning, scheduling This paper we study the partitioning process, and analysis the min-cut algorithm and simulated annealing algorithm.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.3
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• pp.181-187
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• 2020

In this paper, we proposed a register allocation algorithm and resource allocation algorithm in the high level synthesis process for the SoC design synthesis system of high performance vehicles We have analyzed to the operator characteristics and structure of datapath in the most important high-level synthesis. We also introduced the concept of virtual operator for the scheduling of multi-cycle operations. Thus, we demonstrated the complexity to implement a multi-cycle operation of the operator, regardless of the type of operation that can be applied for commonly use in the resources allocation algorithm. The algorithm assigns the functional operators so that the number of connecting signal lines which are repeatedly used between the operators would be minimum. This algorithm provides regional graphs with priority depending on connected structure when the registers are allocated. The registers with connecting structure are allocated to the maximum cluster which is generated by the minimum cluster partition algorithm. Also, it minimize the connecting structure by removing the duplicate inputs for the multiplexor in connecting structure and arranging the inputs for the multiplexor which is connected to the operators. In order to evaluate the scheduling performance of the described algorithm, we demonstrate the utility of the proposed algorithm by executing scheduling on the fifth digital wave filter, a standard bench mark model.