• Title/Summary/Keyword: Process computer

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Optically Controlled Silicon MESFET Modeling Considering Diffusion Process

  • Chattopadhyay, S.N.;Motoyama, N.;Rudra, A.;Sharma, A.;Sriram, S.;Overton, C.B.;Pandey, P.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.7 no.3
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    • pp.196-208
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    • 2007
  • An analytical model is proposed for an optically controlled Metal Semiconductor Field Effect Transistor (MESFET), known as Optical Field Effect Transistor (OPFET) considering the diffusion fabrication process. The electrical parameters such as threshold voltage, drain-source current, gate capacitances and switching response have been determined for the dark and various illuminated conditions. The Photovoltaic effect due to photogenerated carriers under illumination is shown to modulate the channel cross-section, which in turn significantly changes the threshold voltage, drainsource current, the gate capacitances and the device switching speed. The threshold voltage $V_T$ is reduced under optical illumination condition, which leads the device to change the device property from enhancement mode to depletion mode depending on photon impurity flux density. The resulting I-V characteristics show that the drain-source current IDS for different gate-source voltage $V_{gs}$ is significantly increased with optical illumination for photon flux densities of ${\Phi}=10^{15}\;and\;10^{17}/cm^2s$ compared to the dark condition. Further more, the drain-source current as a function of drain-source voltage $V_{DS}$ is evaluated to find the I-V characteristics for various pinch-off voltages $V_P$ for optimization of impurity flux density $Q_{Diff}$ by diffusion process. The resulting I-V characteristics also show that the diffusion process introduces less process-induced damage compared to ion implantation, which suffers from current reduction due to a large number of defects introduced by the ion implantation process. Further the results show significant increase in gate-source capacitance $C_{gs}$ and gate-drain capacitance $C_{gd}$ for optical illuminations, where the photo-induced voltage has a significant role on gate capacitances. The switching time ${\tau}$ of the OPFET device is computed for dark and illumination conditions. The switching time ${\tau}$ is greatly reduced by optical illumination and is also a function of device active layer thickness and corresponding impurity flux density $Q_{Diff}$. Thus it is shown that the diffusion process shows great potential for improvement of optoelectronic devices in quantum efficiency and other performance areas.

Application of Computer-Aided Process Design System for Axisymmetric Deep Drawing Products (축대칭 디프 드로잉 제품에 대한 공정설계 시스템의 적용)

  • Park, S.B.;Park, Y.;Park, J.C.
    • Journal of the Korean Society for Precision Engineering
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    • v.14 no.4
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    • pp.145-150
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    • 1997
  • A computer-aided process design system for axisymmetric deep drawing products has been developed. An approach to the system is based on the knowledge based system. The hypothesized process outline of the deep drawing operations is generated in the geometrical design module of the system. In this paper, the module has been expanded. The rules of process design sechems for complex cup drawings are formulated from handbooks, experimental results and empirical knowhow of the field experts. The input to the system is final sheet-metal objects geometry and the output from the system is process sequence with intermediate objects geometries and process parameters, such as drawing load, blank holding force, clearance and cup-drawing coefficient.

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Application of Process Planning System for Non-Axisymmetric Deep Drawing Products (비축대칭 디프 드로잉 제품에 대한 공정설계 시스템의 적용)

  • 박동환;최병근;박상봉;강성수
    • Transactions of Materials Processing
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    • v.8 no.6
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    • pp.591-603
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    • 1999
  • A computer-aided process planning system for rotationally symmetric deep drawing products has been developed. The application for non-axisymmetric components, however, has been reported yet. Therefore, this study investigates process sequence design in deep drawing process and constructs a computer-aided process planning system for non-axisymmetric motor frame products with elliptical shape. The system developed consists of three modules. The first one os a 3-dimensional modeling module to calculate surface area for non-axisymmetric products. The second one is a blank design module that creates an oval-shaped blank with the identical surface area. The third one is a process planning module based on production rules that play the best important roles in an expert system for manufacturing. The production rules are generated and upgraded by interviewing with field engineers. Especially, drawing coefficient, punch and die radii are considered as main design parameters. The constructed system for elliptical deep drawing products would be very useful to reduce lead time and improve accuracy for production.

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Advanced Business Process Management with Digital Innovations (Review)

  • Masood Ahmed Khalid;Muhammad Jawad Ibrahim
    • International Journal of Computer Science & Network Security
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    • v.23 no.6
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    • pp.121-126
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    • 2023
  • Many organizations are looking for digital innovation to apply in business process management and this information revolution leaves its effect on the businesses and anticipate competitors. In this article, investigates the strength of the relationship between business process management (BMP) and Digital Innovations (DI) since it has been underdeveloped. The results and findings are extracted from international survey with explanations of expert panel to generalized a positive and moderate link of multiple factors that are affecting the strategic decision-making in business process management. It is extended to the Technology Organization Environment (TOE) framework and contour organizations along their Digital Process Innovation (DPI).

A 77 GHz 3-Stage Low Noise Amplifier with Cascode Structure Utilizing Positive Feedback Network using 0.13 μm CMOS Process

  • Lee, Choong-Hee;Choi, Woo-Yeol;Kim, Ji-Hoon;Kwon, Young-Woo
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.4
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    • pp.289-294
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    • 2008
  • A 77 GHz 3-stage low noise amplifier (LNA) employing one common source and two cascode stages is developed using $0.13{\mu}m$ CMOS process. To compensate for the low gain which is caused by lossy silicon substrate and parasitic element of CMOS transistor, positive feedback technique using parasitic inductance of bypass capacitor is adopted to cascode stages. The developed LNA shows gain of 7.2 dB, Sl1 of -16.5 dB and S22 of -19.8 dB at 77 GHz. The return loss bandwidth of LNA is 71.6 to 80.9 GHz (12%). The die size is as small as $0.7mm\times0.8mm$ by using bias line as inter-stage matching networks. This LNA shows possibility of 77 GHz automotive RADAR system using $0.13{\mu}m$ CMOS process, which has advantage in cost compared to sub-100 nm CMOS process.

The Computer Graphic Utilization on the Fashion Design Planning - Focused on the Categorization of Fashion Feeling - (패션디자인 기획의 컴퓨터 그래픽 활용 - 패션 감각 분류를 중심으로 -)

  • Kim, Na-Eun;Cho, Kyu-Hwa
    • Journal of Fashion Business
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    • v.12 no.5
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    • pp.39-53
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    • 2008
  • Today is a 'high concept' era in which consumers make sensible consumption that shares a sensible bond with a brand. Therefore, it is important to analyze consumers' aesthetic awareness; namely, fashion feeling in the fashion industry. This study conducted research into a fashion design planning process according to a fashion feeling focusing on computer graphics suited to the 21st century digital trend. First, the study classified a fashion feeling with eight senses including elegance, classic, modern, mannish, sporty, avant-garde, ethnic, and romantic feelings. Second, the study made an image map, color map, material map, and style map with Adobe Photoshop CS3 by dividing a fashion planning process with a computer graphics program. Also, the study made a flat illustration with Adobe Illustrator CS3. Third, the study proposed the image map, color map, material map, style map, fashion illustration and flat illustration in the design planning process under the theme of the aforementioned eight fashion feelings.

Towards Semantic Healthcare with Interoperable Processes (시맨틱 헬스케어를 위한 상호정보교환 프로세스)

  • Khan, Wajahat Ali;Hussain, Maqbool;Khattak, Asad Masood;Lee, Sung-Young;Gu, Gyo-Ho;Lee, Young-Koo
    • Proceedings of the Korea Information Processing Society Conference
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    • 2011.04a
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    • pp.414-415
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    • 2011
  • Due to heterogeneity in Data and Processes, healthcare systems are facing the challenge of interoperability. This heterogeneity results in different healthcare workflows of each individual organization. The compatibility of these heterogeneous workflows is possible when standards are followed. HL7 is one of the standards that is used for communicating medical data between healthcare systems. Its newer version V3 is providing semantic interoperability which is lacking in V2. The interoperability in HL7 V3 is only limited to data level and process level interoperability needs to be catered. The process level interoperability is achieved only when heterogeneous workflows are aligned. These workflows are very complex in nature due to continuous change in medical data resulting in problems related to maintenance and degree of automation. Semantic technologies plays important role in resolving the above mentioned problems. This research work is based on the integration of semantic technology in HL7 V3 standard to achieve semantic process interoperability. Web Service Modeling Framework (WSMF) is used for incorporating semantics in HL7 V3 processes and achieves seamless communication. Interaction Ontology represents the process artifacts of HL7 V3 and helps in achieving automation.

High $f_T$ 30nm Triple-Gate $In_{0.7}GaAs$ HEMTs with Damage-Free $SiO_2/SiN_x$ Sidewall Process and BCB Planarization

  • Kim, Dae-Hyun;Yeon, Seong-Jin;Song, Saegn-Sub;Lee, Jae-Hak;Seo, Kwang-Seok
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.4 no.2
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    • pp.117-123
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    • 2004
  • A 30 nm $In_{0.7}GaAs$ High Electron Mobility Transistor (HEMT) with triple-gate has been successfully fabricated using the $SiO_2/SiN_x$ sidewall process and BCB planarization. The sidewall gate process was used to obtain finer lines, and the width of the initial line could be lessened to half by this process. To fill the Schottky metal effectively to a narrow gate line after applying the developed sidewall process, the sputtered tungsten (W) metal was utilized instead of conventional e-beam evaporated metal. To reduce the parasitic capacitance through dielectric layers and the gate metal resistance ($R_g$), the etchedback BCB with a low dielectric constant was used as the supporting layer of a wide gate head, which also offered extremely low Rg of 1.7 Ohm for a total gate width ($W_g$) of 2x100m. The fabricated 30nm $In_{0.7}GaAs$ HEMTs showed $V_{th}$of -0.4V, $G_{m,max}$ of 1.7S/mm, and $f_T$ of 421GHz. These results indicate that InGaAs nano-HEMT with excellent device performance could be successfully fabricated through a reproducible and damage-free sidewall process without the aid of state-of-the-art lithography equipment. We also believe that the developed process will be directly applicable to the fabrication of deep sub-50nm InGaAs HEMTs if the initial line length can be reduced to below 50nm order.

A study on the development of standard-time receiving device for process computer (공정용 컴퓨터를 위한 표준시각 수신장치 개발에 관한 연구)

  • 홍용표;손창호
    • 제어로봇시스템학회:학술대회논문집
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    • 1988.10a
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    • pp.592-596
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    • 1988
  • PCS(Process Computer System) is installed to monitor various kinds of process parameters in Power Plant and networked for synthetic monitor and event analysis in all site. But when an event is occured sequentially or simultaneously among the plants, it is difficult to analyze it because of different Standard-Time in each Plant. Standard-Time Receiving Device is developed to solve this problem and development procedure is descried here.

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A study on the development of standard-time receiving device for process computer (공정용 컴퓨터를 위한 표준시각 수신장치 개발에 관한 연구)

  • 홍용표;손창호
    • 제어로봇시스템학회:학술대회논문집
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    • 1988.10a
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    • pp.385-389
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    • 1988
  • PCS(Process Computer System) is installed to monitor various kinds of process parameters in Power Plant and networked for synthetic monitor and event analysis in all site. But when an event is occured sequentially or simultaneously among the plants, it is difficult to analyze it because of different Stardard-Time in each plant. Standard-Time Receiving Device is developed to solve this problem and development procedure is described here.

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