• Journal of the Korean Geographical Society
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• v.45 no.3
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• pp.390-413
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• 2010

Facing reconfiguration of world economic order in the process of globalization and changes in domestic economic and social conditions, Japan has experienced a rapid inflow of foreign immigrants and hence a restructuring of labor market and ethic and cultural mixture. This paper explores contexts of inflow and social and spatial characteristics of immigrant workers in Japan. Uneven regional development on the global level and shifting to flexible accumulation regime, depletion of previously underutilized labor resource, better-educated youth and shrinking and aging of Japanese populace on the national level can be pointed out as important elements of immigration contexts. This paper also explains the hierarchizaton of labor market and differentiation of spatial distribution of immigrant workers in Japan in terms of visa condition and nationality. In particular, focusing on the case of Hiroshima prefecture, this paper analyzes residential differentiation of immigrants according to their nationality. Finally, it finds out some problems which immigrant workers have confronted in Hiroshima region.

• Journal of Distribution Research
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• v.17 no.5
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• pp.39-57
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• 2012

The unabated influx of micro businesses has turned the Korean retailing market to a rat race, which causes severe financial distress for micro business owners due to heavy competition. The woes of these micro business owner's are exacerbated by the presence of large scale distributors such as Super Supermarket(SSM) and large discount stores. In summary, the Korean retail market is overburdened an uneconomically viable. Retailing has low barriers to entry which attracts unskilled labor or those with little capital. These start-ups have low opportunity costs since they would make low wages elsewhere in the economy. Thus, these owners are content with relatively low returns on their investment. These 'subsistence ventures' are maintained for economical viability rather than economic growth. These 'subsistence ventures' intensifies competition among small-scale businesses. The presence of large retail corporations also aggravates the situation. The recent stagnation of the economy has worsened the retail market in Korea. The overwhelming competition solidifies the coarse structural system and the prolonged economic sluggishness has increased the risk of insolvency for micro business owners. As the economy continues to stagnate, the imminent risk in retailing market will rise up to surface threatening economic stability. More systematic inflows and outflows of retailers are required in order to redress this structural problem. It has been empirically shown that the self-employment rate is high in Korea compared to other OECD countries. To draw the comparison of self-employment rate by industry, Korea shows high rates among transportation, whole sale, retail, education, lodging, and restaurants. In the case of the transportation and education service sectors, this high rate can be explained by the idiosyncratic nature of Korean culture. In the transportation sector, political policies favor private cap service and private freight carriers. In the education service sector, Koreans put particular emphasis on education that leads to many private institutions that outnumber other OECD countries. For these singular reasons, Korea maintains high micro business, self-employed rates particularly in retailing. A comparable nation is Japan, with its similar social, economic, cultural environment among OECD countries. Unlike Korea, Japan has much lower rates of micro business which continues to decrease. Also Korean retailers are much more destitute than Japanese. The fundamental problem of Korean retailing is the involuntary exit of these 'subsistence ventures,' micro businesses with low margins, in which a small drop in demand can lead to financial difficulties for the owner. This problem will be exacerbated when Korean babyboomers retire and join the micro business ventures. The first priority in order to cope with the severity of oversupply in retailing is to provide better opportunities for the potential self-employers. There should be viable alternatives to subsistent ventures. Strengthening the retirement program, scrutiny of exit process, reconfiguration of policy funds are the recommendations.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}