• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.5
• /
• pp.564-581
• /
• 2016

We present an efficient hardware prime generator that generates a prime p by combining trial division and Fermat test in parallel. Since the execution time of this parallel combination is greatly influenced by the number k of the smallest odd primes used in the trial division, it is important to determine the optimal k to create the fastest parallel combination. We present probabilistic analysis to determine the optimal k and to estimate the expected running time for the parallel combination. Our analysis is conducted in two stages. First, we roughly narrow the range of optimal k by using the expected values for the random variables used in the analysis. Second, we precisely determine the optimal k by using the exact probability distribution of the random variables. Our experiments show that the optimal k and the expected running time determined by our analysis are precise and accurate. Furthermore, we generalize our analysis and propose a guideline for a designer of a hardware prime generator to determine the optimal k by simply calculating the ratio of M to D, where M and D are the measured running times of a modular multiplication and an integer division, respectively.

• Journal of the Korean Data and Information Science Society
• /
• v.3 no.1
• /
• pp.47-63
• /
• 1992

Bechhofer and Tamhane(1981) proposed Balanced Treatment Incomplete Block (BTIB) desings for comparing p test treatments with a control treatment in blocks of size ${\kappa}$. Notz and Tamhane(1983) solved the problem about determination of the minimal complete class for ${\kappa}=3$. However there are a number of design parameters for which BTIB designs do not exist. We suggest a new class of designs called Group Divisible Treatment Desings(GDTD's) that is a larger class including BTIB designs as a subclass. In this paper we give the minimal complete classes of generator designs for GDTD's with ${\kappa}=2,\;p{\geq}4(except\;prime\;number)\;and\;{\kappa}=3,\;p=4(2)6$.

• KIPS Transactions on Computer and Communication Systems
• /
• v.4 no.10
• /
• pp.337-342
• /
• 2015

We develop a new parallelization method for Sieve of Eratosthenes algorithm, which enhances both computation speed and energy efficiency. A pipeline scheduling is included for better load balancing after proper workload partitioning. They run on multicore CPUs with hybrid parallel programming model which uses both message passing and multithreading computation. Experimental results performed on both small scale clusters and a PC with a mobile processor show significant improvement in execution time and energy consumptions.

• International Journal of Computer Science & Network Security
• /
• v.23 no.7
• /
• pp.49-60
• /
• 2023

The amount of data generated by electronic systems through e-commerce, social networks, and data computation has risen. However, the security of data has always been a challenge. The problem is not with the quantity of data but how to secure the data by ensuring its confidentiality and privacy. Though there are several research on cloud data security, this study proposes a security scheme with the lowest execution time. The approach employs a non-linear time complexity to achieve data confidentiality and privacy. A symmetric algorithm dubbed the Non-Deterministic Cryptographic Scheme (NCS) is proposed to address the increased execution time of existing cryptographic schemes. NCS has linear time complexity with a low and unpredicted trend of execution times. It achieves confidentiality and privacy of data on the cloud by converting the plaintext into Ciphertext with a small number of iterations thereby decreasing the execution time but with high security. The algorithm is based on Good Prime Numbers, Linear Congruential Generator (LGC), Sliding Window Algorithm (SWA), and XOR gate. For the implementation in C, thirty different execution times were performed and their average was taken. A comparative analysis of the NCS was performed against AES, DES, and RSA algorithms based on key sizes of 128kb, 256kb, and 512kb using the dataset from Kaggle. The results showed the proposed NCS execution times were lower in comparison to AES, which had better execution time than DES with RSA having the longest. Contrary, to existing knowledge that execution time is relative to data size, the results obtained from the experiment indicated otherwise for the proposed NCS algorithm. With data sizes of 128kb, 256kb, and 512kb, the execution times in milliseconds were 38, 711, and 378 respectively. This validates the NCS as a Non-Deterministic Cryptographic Algorithm. The study findings hence are in support of the argument that data size does not determine the execution.

• Korean Journal of Mathematics
• /
• v.21 no.4
• /
• pp.365-374
• /
• 2013

Let $k=\mathbb{F}_q(T)$ be a rational function field over the finite field $\mathbb{F}_q$, where q is a power of an odd prime number, and $\mathbb{A}=\mathbb{F}_q[T]$. Let ${\gamma}$ be a generator of $\mathbb{F}^*_q$. Let $\mathcal{H}_n$ be the subset of $\mathbb{A}$ consisting of monic square-free polynomials of degree n. In this paper we obtain an asymptotic formula for the mean value of $L(1,{\chi}_{\gamma}{\small{D}})$ and calculate the average value of the ideal class number $h_{\gamma}\small{D}$ when the average is taken over $D{\in}\mathcal{H}_{2g+2}$.

• Bulletin of the Korean Mathematical Society
• /
• v.55 no.6
• /
• pp.1627-1638
• /
• 2018

In this paper, we study an special type of cyclic codes called skew cyclic codes over the ring ${\mathbb{F}}_p+v{\mathbb{F}}_p+v^2{\mathbb{F}}_p$, where p is a prime number. This set of codes are the result of module (or ring) structure of the skew polynomial ring (${\mathbb{F}}_p+v{\mathbb{F}}_p+v^2{\mathbb{F}}_p$)[$x;{\theta}$] where $v^3=1$ and ${\theta}$ is an ${\mathbb{F}}_p$-automorphism such that ${\theta}(v)=v^2$. We show that when n is even, these codes are either principal or generated by two elements. The generator and parity check matrix are proposed. Some examples of linear codes with optimum Hamming distance are also provided.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.24 no.11
• /
• pp.1470-1476
• /
• 2020

This paper describes a design of a lightweight security system-on-chip (SoC) suitable for the implementation of security protocols for IoT and mobile devices. The security SoC using Cortex-M0 as a CPU integrates hardware crypto engines including an elliptic curve cryptography (ECC) core, a SHA3 hash core, an ARIA-AES block cipher core and a true random number generator (TRNG) core. The ECC core was designed to support twenty elliptic curves over both prime field and binary field defined in the SEC2, and was based on a word-based Montgomery multiplier in which the partial product generations/additions and modular reductions are processed in a sub-pipelining manner. The H/W-S/W co-operation for elliptic curve digital signature algorithm (EC-DSA) protocol was demonstrated by implementing the security SoC on a Cyclone-5 FPGA device. The security SoC, synthesized with a 65-nm CMOS cell library, occupies 193,312 gate equivalents (GEs) and 84 kbytes of RAM.