• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2C
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• pp.1-9
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• 2005

Code is a set of words. If, for any pair of words in the code, one is not prefix of another, the code is called "Prefix(-Free) Code". The prefix coding problem is, given n, to find an optimal code with the minimum-sum of lengths of n words. As a special case of this, we present a method to find, given language L in some specific classes of regular languages, an optimal code among prefix codes in L. We also show how the structure of optimal codes varies as n grows, using trees.

• Journal of Digital Contents Society
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• v.18 no.3
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• pp.613-619
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• 2017

This paper presents a CUDA (Compute Unified Device Architecture) code to achieve correct GPU parallel segmented prefix operation results with less than 32 segment length for large data arrays. Mark Harris and Michael Garland had published CUDA code to address the tasks. This paper shows that their code does not generate correct results when the local segment length is less than 32, discusses the cause of the problem, and presents a CUDA code that generates correct results. The segmented parallel prefix operation presented in this paper can be applied as a building block to various large parallel processing algorithms including the k-nearest neighbor search problems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.1
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• pp.38-46
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• 1992

In this thesis, a high speed code synchronization circuit is implemented, which is applicable to frequency hopping FSK tranceiver within 68-88 MIBz band- width. synchronization Process consists of two steps, initial synchronization and tracking. A modified matched filter method using two channel passive correlators matched with short hopping frequencies, synchronization prcfix. is proposed for initial synchronization. To increase probability of initial synchronization, prefix are transmitted repeatedly. The outputs of correlators are sent to synchronization decision circuit, and code start time Is extracted by synchronizatlon decision circuit-Modified matched fitter method makes it possible to reduce complexity in hardware and obtain code acquisition rapidly.Clock recovery circuit regenerates PN code clock for tracking.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.8
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• pp.1543-1548
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• 2009

In this paper, a high speed code synchronization circuit is proposed. for fast code synchronization, matched filler method is used for initial code acquisition with two channel correlators. Particular frequency patterns of the limited number having the information about PN code start time are composed and transmitted repeatedly to increase the probability of accurate initial synchronization. And digital frequency synthesizer is proposed. And it's performance is analyzed theoretically. The analysis show that fast frequency hopping is possible in frequency hopping system that use digital frequency synthesizer.

• Proceedings of the Korean Society for Information Management Conference
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• 2000.08a
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• pp.63-66
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• 2000

본 연구는 인터넷상에서 제공되는 지적콘텐츠에 대한 영속적이고 고유한 식별 체계인 DOI 상용 서비스의 일환으로 DOI 구문을 구성하고 있는 Prefix와 Suffix 식별코드를 개발하였다. 이를 위해서 현재 인터넷상에서 지적콘텐츠를 유통시키고 있는 기관들을 조사 분류하여 콘텐츠 보유기관 식별코드를 개발하였다. 또한 지적콘텐츠의 속성 및 유형 분석을 토대로 Suffix 코드의 구조 및 식별코드를 개발하였으며 관련 콘텐츠간의 연계를 위한 저작권 식별기호를 고려하였다.

• Journal of Satellite, Information and Communications
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• v.6 no.1
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• pp.86-96
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• 2011

In this paper we propose a Pre-rake system applied with a frequency domain equalizer in TDD/CDMA multi-code transmission. The Pre-rake system has been well known technique in TDD/CDMA to make a receiver simple. However, it still has residual losses of path diversity and signal to noise ratio (SNR). However, gathering all the residual paths demands an additional hardware such as a rake combiner at the receiver. For the reason Pre/Post-rake system has already been proposed at up/downlink correlated channel conditionunder the assumption of noisier channel. There is a trade-off between the first purpose of Pre-rake that makes hardware simple at the receiver and the performance improvement. From the point the frequency domain equalizer (FDE) can be considered in Pre/Post-rake to supply the receiver with the flexible equalizing methods with rather reduced complexity compared with time domain rake combiner or equalizers. Pre-rake itself increases the number of multipath, which results from the convolution of Pre-rake filter and wireless channel, and FDE must be well matched to Pre/Post-rake, while it considers the relationship of hardware complexity and the performance. In this paper, the Pre-rake/Post-FDE system is introduced at TDD/CDMA multi-code transmission. In addition, the cyclic prefix reduction method in the proposed system is introduced, and the theoretical analysis to the proposed system is given by assuming Gaussian approximation, and finally the numerical simulation results are provided.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11A
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• pp.1087-1094
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• 2008

In this paper, we propose the acquisition method of the Cyclic-Prefix CDMA using Good-Autocorrelation-Sequence (GAS-CP-CDMA) system. The sequences for GAS-CP-CDMA are m-sequence and constant amplitude zero autocorrelation code (CAZAC) with good autocorrelation property. The GAS-CP-CDMA system is proposed for interference cancellation in multi-user and -path environment in co-cell. However, the reliable initial acquisition in multi-path fading channel and multi-user system environment is crucial. In this paper, non-coherent power detector and threshold value are used for discriminating signal acquisition. The sequence used for computer simulation is CAZAC. The simulation results show proper threshold value depends on the number of users. Through the computer simulation, we draw setting up method of the optimum threshold value for the GAS-CP-CDMA system.

• Journal of the Korea Society of Computer and Information
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• v.19 no.12
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• pp.111-121
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• 2014

In this paper, we propose tree-based hybrid query tree architecture utilizing time slot. 4-Bit Pattern Slot Allocation(4-SL) has a 8-ary tree structure and when tag ID responses according to query of the reader, it applies a digital coding method, the Manchester code, in order to extract the location and the number of collided bits. Also, this algorithm can recognize multiple Tags by single query using 4 fixed time slots. The architecture allows the reader to identify 8 tags at the same time by responding 4 time slots utilizing the first bit($[prefix+1]^{th}$, F ${\in}$ {'0' or '1'}) and bit pattern from second ~ third bits($[prefix+2]^{th}{\sim}[prefix+3]^{th}$, $B_2{\in}$ {"00" or "11"}, $B_1{\in}$ {"01" or "10"}) in tag ID. we analyze worst case of the number of query nodes(prefix) in algorithm to extract delay time for recognizing multiple tags. The identification delay time of the proposed algorithm was based on the number of query-responses and query bits, and was calculated by each algorithm.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.11
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• pp.7456-7462
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• 2015

This paper proposes a spectral efficient space-frequency(SF) block coded single carrier-frequency division multiple access(SC-FDMA) transmission system in a relaying multi-path shadow area. The cyclic prefix(CP) is not used in the proposed system in order to prevent a loss of spectral efficiency due to the use of CP. The destruction of channel cyclicity due to the lack of CP is recovered at the receivers of relays and a destination station. Simulation results show that the performance of the proposed system without CP is almost same as that of the conventional system with full CP, thus increasing the spectral efficiency.

• Convergence Security Journal
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• v.7 no.2
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• pp.129-134
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• 2007

This paper proposes multiple burst error detection and correction scheme for transmission of Huffman coded string. We use bidirectionally decodable codes and introduce insertion of forbidden symbol to find errors. Additional bits are added to original bit streams to correct errors. The total file size id increased but it can detect errors and recover errors real time.