• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.148-158
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• 2012

This paper presents the design of the incremental delta-sigma ADC. The proposed circuit consists of pre-amplifier, S & H circuit, MUX, delta-sigma modulator, and decimation filter. Third-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a $0.18{\mu}m$ CMOS technology. The designed circuit show that the modulator achieves 87.8 dB signal-to-noise and distortion ratio (SNDR) over a 5 kHz signal bandwidth and differential nonlinearity (DNL) of ${\pm}0.25$ LSB, integral nonlinearity (INL) of ${\pm}0.2$ LSB. Power consumption of delta-sigma modulator is $941.6{\mu}W$. It was decided that N cycles are 200 clock for 16-bits output.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.6
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• pp.835-840
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• 1993

In this paper a FET mixer is designed realized by small-signal S-parameter using microwave CAD, LINMIC + at Ku-band. The mixer has conversion gain 9.88dB at 14GHz RF, 1GHz IF, and + 1dBm LO imput. The maximum conversion gain is obtained 11.71dB at 1.1GHz. The result shows that the FET mixer does not need pre-and/or IF amplifier. The mixer maintains the desired conversion gain with low LO power level. The conversion gain of the mixer is higher than the available gain of a amplifier, which is experimentally verified.

• Proceedings of the KOSOMBE Conference
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• v.1995 no.11
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• pp.86-89
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• 1995

A clinically oriented 32 channel Electroencephalogram (EEG) and evoked potential (EP) mapping system has been developed. The EEG and EP signals acquired from 32-channel electrodes are amplified by the pre-amplifier located near patient and are then tither amplified by main amplifier. An automatic artifact rejection scheme is employed using a neural network by which examination time is reduced substantially. Auditary and visual stimuli are used for the evoked potential mapping. A user-friendly graphical interface based on the Microsoft Window 3.1 is developed for the operation of the system. Statistical databases for the poop and individual comparisons are also included to support statistically based diagnosis.

• Journal of the Optical Society of Korea
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• v.16 no.1
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• pp.1-5
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• 2012

This paper describes a 150-Mb/s monolithic optical receiver for plastic optical fiber link using a standard CMOS technology. The receiver integrates a photodiode using an N-well/P-substrate junction, a pre amplifier, a post amplifier, and an output driver. The size, PN-junction type, and the number of metal fingers of the photodiode are optimized to meet the link requirements. The N-well/P-substrate photodiode has a 200-${\mu}m$ by 200-${\mu}m$ optical window, 0.1-A/W responsivity, 7.6-pF junction capacitance and 113-MHz bandwidth. The monolithic receiver can successfully convert 150-Mb/s optical signal into digital data through up to 30-m plastic optical fiber link with -10.4 dBm of optical sensitivity. The receiver occupies 0.56-$mm^2$ area including electrostatic discharge protection diodes and bonding pads. To reduce unnecessary power consumption when the light is not over threshold or not modulating, a simple light detector and a signal detector are introduced. In active mode, the receiver core consumes 5.8-mA DC currents at 150-Mb/s data rate from a single 3.3 V supply, while consumes only $120{\mu}W$ in the sleep mode.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.85-90
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• 2009

This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ${\mu}m$ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 mA at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 $\times$ 2.8 $mm^{2}$.

• Nuclear Engineering and Technology
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• v.37 no.3
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• pp.279-286
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• 2005

A prototype of a relativistic proton generation system, based on laser-induced plasma interaction, has been designed and fabricated. The system is composed of three major parts: a fs TW laser; a target chamber, including targets and controls; and a diagnostic system for charged particles and lasers. An Offner-type pulse stretcher for chirped pulse amplification (CPA) and eight pass pre-amplifier are installed. The main amplifier will be integrated with a new pumping laser. The design values of the laser at the first stage are 1 TW in power and 50 fs in pulse duration. We expect to generate protons with their maximum energy of approximately 3 MeV and the flux of at least $10^6$ per pulse using a 10 $\mu$m Al target. A prototype target chamber with eight 8-inch flanges, including target mounts, has been designed and fabricated. For laser diagnostics, an adaptive optics based on the Shack-Hartmann type, beam monitoring, and alignment system are all under development. For a charged particle, CR-39 detectors, a Thomson parabola spectrometer, and Si charged-particle detectors will be used for the density profile and energy spectrum. In this paper, we present the preliminary design for laser-induced proton generation. We also present plans for future work, as well as theoretical simulations.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.8
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• pp.79-86
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• 1999

A simulation of 10 Gbps optical fiber transmission system using DCf(dispersion compensating fiber) for the dispersion compensation is performed. In order to analyze the NRZ pulse propagation in nonlinear, dispersive and lossy fiber, the split-step finite element method that is combination of finite element method and finite difference method is used. Also, we obtained the optical eye diagram and BER characteristics at the receiver of the system that is contained the optical amplifier and system noises. As a result of simulation, we obtain that the dispersion penalty is about 0.8dB after 50km transmission and the receiver sensitivities at $10^{-9}$ BER are -27.4dBm with EDFA pre-amplifier of 12dB gain and -15.6dBm without EDFA.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.9
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• pp.915-921
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• 2013

This work presents a 77 GHz low noise amplifier(LNA) for automotive radar systems using 65 nm RF CMOS process. The LNA is composed of three stage common source amplifiers and includes transmission line matching networks. To reduce the time for three dimensional EM simulation, we optimize the transmission line impedance matching network using a pre-built EM library. The proposed compact simulation technique is confirmed by measurement results. The peak gain of the LNA is 10 dB at 77 GHz and input/output return losses are below -10 dB around the design frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.3
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• pp.312-319
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• 2011

In this paper, a new linearization algorithm for DPD(Digital PreDistorter) is suggested. This new algorithm uses DFP(Davidon-Fletcher-Powell) method. This algorithm is more accurate than that of the existing algorithms, and this method renew the best-fit value in every routine with out setting the initial value of step-size. In modeling power amplifier, the memory polynomial model which can model the memory effect of the power amplifier is used. And the overall structure of linearizer is based on an indirect learning architecture. In order to verify for performance of proposed algorithm, we compared with LMS(Least Mean-Squares), RLS(Recursive Least squares) algorithm.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.3
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• pp.1-7
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• 2014

This paper describes the implementation of high speed comparator for the ATE (automatic test equipment) system. The comparator block is composed of continuous comparator, differential difference amplifier(DDA) and output stage. For the wide input dynamic range of 0V to 5V, and for the high speed operation (1~800MHz), high speed rail-to-rail amplifier is used in the first stage. And hysteresis circuits, pre-amp and latch are followed for high speed operation. To measure the difference of output signals between the two devices under test (DUTs), a DDA is applied because it can detect the differences of both common signals and differential signals. This comparator chip was implemented with $0.18{\mu}m$ BCDMOS process and can compare the signal difference of 5mV up to the frequency range of 800 MHz. The chip area of the comparator is $620{\mu}m{\times}830{\mu}m$.