• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.12-19
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• 1997

In this paper, we present a logic synthesis algorithm for low powr design fo combinational circuits. The proposed algorithm reduces power dissipation by eliminating unnecessary signal transitions. The proposed algorithm restructures a given circuit by using a kernel as prediction logic in a precomputation-based scheme such that switching activity of circuit can be minimized. Experimental results show that the system is efficient for low power design of combinational circuits.

• Proceedings of the KIEE Conference
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• summer
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• pp.1263-1265
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• 2004

RF-ID system is one of the very interesting field not only in a technical and economical point of view but also that people are still trying to realize lossless power transmission. This paper has a purpose on the efficient power transmission at the passive type IDcard by using wireless power transmission system. The most difficult but important part of the passive type RF-ID system is building the system that supplies power from Reader-antenna to IDcard-antenna. To check what is the most efficient way to deliver power depending on what kind of specifications of the power-amp in reader, antenna and antenna in IDcard is for operating IDcard circuit efficiently receiving the power from reader-antenna. For this, we used 125kHz sinewave for RF signal as a basic specification, OP-amp for amplifying signal and power-amp for amplifying power, loop type antenna.

• Proceedings of the KIEE Conference
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• 1995.07a
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• pp.198-201
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• 1995

The overall design criteria for the optimal design of a small LEO satellite power system are described in summary. The analysis result of the KITSAT-I whole orbit data suggests the efficient power opertion for KITSAT-I and also gives some crutial information for developing a new satellite power system.

• Journal of electromagnetic engineering and science
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• v.17 no.4
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• pp.221-227
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• 2017

A new approach to designing a broadband and highly efficient class-E power amplifier based on nonlinear shunt capacitance analysis is proposed. The nonlinear shunt capacitance method accurately extracts optimum class-E power amplifier parameters, including an external shunt capacitance and an output impedance, at different frequencies. The dependence of the former parameter on the frequency is considered to select an optimal value of external shunt capacitor. Then, upon determining the latter parameter, an output matching network is optimized to obtain the highest efficiency across the bandwidth of interest. An analytical approach is presented to design the broadband class-E power amplifier of a MOSFET transistor. The proposed method is experimentally verified by a 140-170 MHz class-E power amplifier design with maximum added power efficiency of 82% and output power of 34 dBm.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.301-302
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• 2007

Maximum power consumption was up to 6,228kW in the summer of 2007 due to steady development of industry as well as increased demand of individual. Twenty fossil-Fired Thermal Power Plant for 500MW were underconstructed at present. KEPRI(Korea Electric Power Research Institute) manage 'Development of Advanced Fossil-Fired Thermal Power Generation System' project to construct high efficient power plant of 1000MW capacity for preparing increased demand of power. Design of control logic and data sampling were explained and high efficient control logic was simulated in detail in 'The Development of Next Generation Power Plant Instrument and Control System'(sub-project of 'Development of Advanced Fossil-Fired Thermal Power Generation System' project).

• Journal of Power Electronics
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• v.13 no.3
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• pp.458-468
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• 2013

Large capacity reactive power compensation and harmonic control in the low-voltage grid of an enterprise, are important technical means to improve power quality and reduce power loss. In this paper, the principle of an efficient power quality controller is analyzed. Then, key application technologies of the HPQC which would influence the performances of the HPQC are studied. Based on an analysis of the harmonic shunt problem, a frequency dividing control strategy of the HPQC continuous subsystem is proposed. A parameter design method of the HPQC discrete subsystem and its installation method are also proposed to ensure the system compensation effect. HPQC systems have been designed for a copper foil plant. The effectiveness of this paper has been verified by the simulation and application results.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.12
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• pp.2337-2343
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• 2010

AMR(Automatic Meter Reading)/AMI(Advanced Metering Infrastructure) is actively deployed all over the world. efficient, economical, stable and reliable system need to push forward the AMR/AMI business, so various researchs are in progress. In electric power system of domestic, a transformer is connected average twenty to thirty households and PLC is possible to communication within household connected same transformer. So if server and data concentrator unit(DCU) share circuit line through communication between transformers, communication network is able to efficient. Therefore we design new communication method between DCUs and test it and demonstrate the performance.

• ETRI Journal
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• v.35 no.2
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• pp.253-258
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• 2013

We propose and demonstrate an efficient power-saving optical network unit (ONU) based on upstream traffic monitoring for 10-Gb/s wavelength division multiplexed passive optical networks (WDM-PONs). The power-saving mode controller uses a ${\mu}$-processor and traffic monitoring modules followed by the proposed power-saving processes to operate the sleep mode ONU. The power consumption of the ONU is effectively reduced from 19.3 W to 6.4 W when no traffic from the users is detected. In addition, we design a power-saving mechanism based on a cyclic sleep mode operation to allow a connectivity check between the optical line terminal and ONU. Our calculation results show that the WDM-PON ONU reduces the power consumption by around 60% using the proposed mechanism.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.5
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• pp.116-124
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• 2012

In this paper, we propose an efficient lighting control system design for AVR based LSDM control. This paper, an efficient lighting control system design for LSDM control be design divided as the signal control part for I/O data bus and the timer/counter part for clock signal control according to operating conditions. LSDM control logic be optimization to PORTx and DDRx register by specifying the logical value of each bit for effective control signal processing. And, the LSDM control signal by lighting control program execution of ATmega128 be designed to be LSDM lighting control by control logic operating. In this paper, a proposed lighting control system were measured to power loss rate to proved the power loss reduction about lighting status of LSDM control logic by download the lighting control program to system through serial from host PC. As a measurement result, a proposed lighting control system than the existing lighting control system were proved to be effective to the overall power consumption reduction.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.605-614
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• 2016

We develop a novel SAD circuit for power-efficient H.264 encoding, namely a-SAD. Here, some highest-order MSB's are approximated to single MSB. Our theoretical estimations show that our proposed design simultaneously improves performance and power of SAD circuit, achieving good power efficiency. We decide that the optimal number of approximated MSB's is four under 8-bit YUV-420 format, the largest number not to affect video quality and compression-rate in our video experiments. In logic simulations, our a-SAD circuit shows at least 9.3% smaller critical-path delay compared to existing SAD circuits. We compare power dissipation under iso-throughput scenario, where our a-SAD circuit obtains at least 11.6% power saving compared to other designs. We perform same simulations under two- and three-stage pipelined architecture. Here, our a-SAD circuit delivers significant performance (by 13%) and power (by 17% and 15.8% for two and three stages respectively) improvements.