• ETRI Journal
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• v.30 no.3
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• pp.451-460
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• 2008

Recently, the power consumption of integrated circuits has been attracting increasing attention. Many techniques have been studied to improve the power efficiency of digital signal processing units such as fast Fourier transform (FFT) processors, which are popularly employed in both traditional research fields, such as satellite communications, and thriving consumer electronics, such as wireless communications. This paper presents solutions based on parallel architectures for high throughput and power efficient FFT cores. Different combinations of hybrid low-power techniques are exploited to reduce power consumption, such as multiplierless units which replace the complex multipliers in FFTs, low-power commutators based on an advanced interconnection, and parallel-pipelined architectures. A number of FFT cores are implemented and evaluated for their power/area performance. The results show that up to 38% and 55% power savings can be achieved by the proposed pipelined FFTs and parallel-pipelined FFTs respectively, compared to the conventional pipelined FFT processor architectures.

• Proceedings of the KIEE Conference
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• 2002.06a
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• pp.79-82
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• 2002

Non-linear loads are the sources of power systems harmonics, and the power quality is influenced by harmonics, Recently, the requirements of power quality is important. For the power quality problems. it is very important that the development of power measurement circuit for non-linear load. In this paper, it is discoursed on that high speed sampling circuit and efficient power analysis algorithms. The sampling circuit is implemented using FPGA. Since the power measurement circuit system is composed by FPGA and efficient power algorithms. it is practicable application that accurate power measurement, stable protection relaying, and low cost system configuring.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.3
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• pp.211-218
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• 2005

Switched Reluctance Motor(SRM) offers the advantages of simple and robust motor construction, high speed and high efficiency over a wide operating range of torque and speed, excellent controllability. However SRM has the disadvantages of high current harmonics, and low power factor because the required output of speed and torque is produced by the discontinuous and loss of power system, and brings about the incorrect operation of electronic system. This paper deals with an energy efficient converter fed SRM system with the reduced harmonics and improved power factor. The validity of the proposed scheme is verified via experiments. We are implemented the proposed control system using 80C196KC micro-controller.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.5
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• pp.606-612
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• 2012

A highly efficient multi-mode balanced power amplifier(PA) structure is proposed for W-CDMA handset applications. The proposed PA has 2-stage amplifier configuration and the stage-bypass and load impedance switching techniques were applied to enhance power efficiency at medium power level as well as low output power level. Using the two techniques, four highly efficient power modes were realized. To demonstrate the usefulness of the proposed structure, a GaAs HBT balanced PA module was designed, fabricated, and measured.

• ETRI Journal
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• v.37 no.1
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• pp.107-117
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• 2015

This paper presents an energy-efficient (low power) prime-field hyperelliptic curve cryptography (HECC) processor with uniform power draw. The HECC processor performs divisor scalar multiplication on the Jacobian of genus 2 hyperelliptic curves defined over prime fields for arbitrary field and curve parameters. It supports the most frequent case of divisor doubling and addition. The optimized implementation, which is synthesized in a $0.13{\mu}m$ standard CMOS technology, performs an 81-bit divisor multiplication in 503 ms consuming only $6.55{\mu}J$ of energy (average power consumption is $12.76{\mu}W$). In addition, we present a technique to make the power consumption of the HECC processor more uniform and lower the peaks of its power consumption.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.301-302
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• 2007

Maximum power consumption was up to 6,228kW in the summer of 2007 due to steady development of industry as well as increased demand of individual. Twenty fossil-Fired Thermal Power Plant for 500MW were underconstructed at present. KEPRI(Korea Electric Power Research Institute) manage 'Development of Advanced Fossil-Fired Thermal Power Generation System' project to construct high efficient power plant of 1000MW capacity for preparing increased demand of power. Design of control logic and data sampling were explained and high efficient control logic was simulated in detail in 'The Development of Next Generation Power Plant Instrument and Control System'(sub-project of 'Development of Advanced Fossil-Fired Thermal Power Generation System' project).

• KIEE International Transactions on Electrophysics and Applications
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• v.4C no.3
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• pp.101-105
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• 2004

The efficient power MOSFET inverter applied for a simple and low cost power supply is proposed for driving the dielectric barrier discharge (DBD) lamp load. For decades, the DBD phenomenon has been used for ozone gas production in industry. In this research, the ultraviolet and visible light sources utilizing the DBD lamp is considered as the load for solid-state high frequency power supply. It is found that the simple voltage-source single-ended quasi-resonant ZVS inverter with only one active power switch could effectively drive this load with the output power up to 700 W. The pulse density modulation based control scheme for the single-ended quasi-resonant ZVS inverter using a low voltage and high current power MOSFET switching device is proposed to provide a linear power regulation characteristic in the wide range 0-100％ of the full power as compared with the conventional control based Royer type parallel resonant inverter type power supplies.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.1
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• pp.41-46
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• 2012

In this paper, An efficient circuit design algorithm considering constraint is proposed. The proposed algorithm sets up in time constraint and area constraint, power consumption constraint for a circuit implementation. First, scheduling process for time constraint. Select the FU(Function Unit) which is satisfied with time constraint among the high level synthesis results. Analyze area and power consumption of selected FUs. Constraint set for area and power constraint. Device selection to see to setting condition. Optimization circuit implementation in selected device. The proposed algorithm compared with [7] and [8] algorithm. Therefore the proposed algorithm is proved an efficient algorithm for optimization circuit implementation.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.3
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• pp.227-232
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• 2014

A highly efficient MOSFET inverter for single-phase grid-connected photovoltaic power generation systems is presented in this paper. It is a full-MOSFET version of the conventional transformerless full-bridge inverter with dual L-C filters using unipolar PWM. The key idea lies on smart pre switching(SPS), which can make the large switching loss due to a poor reverse recovery of the MOSFET's body diode reduced dramatically. The validity of the proposed inverter is verified by experiment.

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.1187-1188
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• 2006

This paper a new method which applies a genetic algorithm for determining which sectionalizing switch to operate in order to solve the distribution system loss minimization re-configuration problem. In addition, the proposed method introduces a ultra efficient MPP tracking in a solar power generation system.