• Fire Science and Engineering
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• v.20 no.1 s.61
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• pp.71-76
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• 2006

The major causes of electrical fire are classified to short circuit fault, overload fault, electric leakage and electric contact failure. The occurrence factor of the fire is electric arc or spark accompanied with electrical faults. Residual Current Protective Device(RCD) of high sensitivity type used at low voltage wiring cuts off earth leakage and overload, but the RCD can't cut off electric arc or spark to be a major factor of electrical fire. As the RCDs which are applied low voltage distribution panel are prescribed to rated breaking time about 30[ms](KS C 4613), the RCDs can't perceive to the periodic electric arc or spark of more short wavelength level. To be improved on such problem, this paper is proposed to a auxiliary control apparatus for RCD trip on electric arc or spark due to electrical fire. Some experimental results of the proposed apparatus is confirmed to the validity of the analytical results.

• Korean Journal of Materials Research
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• v.22 no.11
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• pp.636-641
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• 2012

In this study, we have investigated highly efficient nanoscale surface corrugated light emitting diodes (LEDs) for the enhancement of light extraction efficiency (LEE) of nitride semiconductor LEDs. Nanoscale indium tin oxide (ITO) surface corrugations are fabricated by using the conformal nanoimprint technique; it was possible to observe an enhancement of LEE for the ITO surface corrugated LEDs. By incorporating this novel method, we determined that the total output power of the surface corrugated LEDs were enhanced by 45.6% for patterned sapphire substrate LEDs and by 41.9% for flat c-plane substrate LEDs. The enhancement of LEE through nanoscale surface corrugations was studied using 3-dimensional Finite Different Time Domain (FDTD) calculation. From the FDTD calculations, we were able to separate the light extraction from the top and bottom sides of device. This process revealed that light extraction from the top and bottom sides of a device strongly depends on the substrate and the surface corrugation. We found that enhanced LEE could be understood through the mechanism of enhanced light transmission due to refractive index matching and the increase of light scattering from the corrugated surface. LEE calculations for the encapsulated LEDs devices also revealed that low LEE enhancement is expected after encapsulation due to the reduction of the refractive index contrast.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.4
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• pp.641-648
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• 2023

Recently, the rapid growth of artificial intelligence among the 4th industrial revolution has progressed based on the performance improvement of semiconductor, and circuit integration. According to transistors, which help operation of internal electronic devices and equipment that have been progressed to be more complicated and miniaturized, the control of heat generation and improvement of heat dissipation efficiency have emerged as new performance indicators. The DUT(Device Under Test) Shell is equipment which detects malfunction transistor by evaluating the durability of transistor through heat dissipation in a state where the power is cut off at an arbitrary heating point applying the rating current to inspect the transistor. Since the DUT shell can test more transistor at the same time according to the heat dissipation structure inside the equipment, the heat dissipation efficiency has a direct relationship with the malfunction transistor detection efficiency. Thus, in this paper, we propose various method for PCB configuration structure to optimize heat dissipation of DUT shell and we also propose various transformation and thermal analysis of optimal DUT shell using computational fluid dynamics.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.1
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• pp.75-80
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• 2009

Bum-in test is one for eliminating semiconductor devices that are subject to early failures and other operational problems; it is usually carried out on the devices by imposing severe test conditions such as elevated voltages, temperatures, and time. In order for such a test to be performed, each burn-in board having devices to be tested, needs to be inserted into a corresponding slot. A set of such slots is called a zone. The slots comprising a zone can only have the burn-in boards with the devices of the same type. In order to test many different types of semiconductor devices, it is desirable to build a burn-in test system to have as many zones as possible. A zone controller controlling a zone, is a device that performs a burn-in test and collects test results. In case of existing systems, each zone controller takes care of a zone that consists of a fixed number of slots. Since a zone controller is, in most cases, embedded into a workstation that controls the overall testing process, adding new zone controllers is restricted by the spaces for them. As a way to solve or alleviate these problems, a dynamic zone system in which the number of slots in a zone can be dynamically allocated, is presented. This system maximizes the efficiency of system utilization, by altering the number of slots and hence minimizing the idle slots of a zone. In addition, all the test operations being performed must be aborted for maintenance in existing systems. In dynamic zone systems, however, a separate and independent maintenance is allowed for each slot, as long as the main power supply system has no problem.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.189-189
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• 2012

Lead sulfide (PbS) nanocrystal quantum dots (NQDs) are promising materials for various optoelectronic devices, especially solar cells, because of their tunability of the optical band-gap controlled by adjusting the diameter of NQDs. PbS is a IV-VI semiconductor enabling infrared-absorption and it can be synthesized using solution process methods. A wide choice of the diameter of PbS NQDs is also a benefit to achieve the quantum confinement regime due to its large Bohr exciton radius (20 nm). To exploit these desirable properties, many research groups have intensively studied to apply for the photovoltaic devices. There are several essential requirements to fabricate the efficient NQDs-based solar cell. First of all, highly confined PbS QDs should be synthesized resulting in a narrow peak with a small full width-half maximum value at the first exciton transition observed in UV-Vis absorbance and photoluminescence spectra. In other words, the size-uniformity of NQDs ought to secure under 5%. Second, PbS NQDs should be assembled carefully in order to enhance the electronic coupling between adjacent NQDs by controlling the inter-QDs distance. Finally, appropriate structure for the photovoltaic device is the key issue to extract the photo-generated carriers from light-absorbing layer in solar cell. In this step, workfunction and Fermi energy difference could be precisely considered for Schottky and hetero junction device, respectively. In this presentation, we introduce the strategy to obtain high performance solar cell fabricated using PbS NQDs below the size of the Bohr radius. The PbS NQDs with various diameters were synthesized using methods established by Hines with a few modifications. PbS NQDs solids were assembled using layer-by-layer spin-coating method. Subsequent ligand-exchange was carried out using 1,2-ethanedithiol (EDT) to reduce inter-NQDs distance. Finally, Schottky junction solar cells were fabricated on ITO-coated glass and 150 nm-thick Al was deposited on the top of PbS NQDs solids as a top electrode using thermal evaporation technique. To evaluate the solar cell performance, current-voltage (I-V) measurement were performed under AM 1.5G solar spectrum at 1 sun intensity. As a result, we could achieve the power conversion efficiency of 3.33% at Schottky junction solar cell. This result indicates that high performance solar cell is successfully fabricated by optimizing the all steps as mentioned above in this work.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.993-994
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• 2008

Electrochromic (EC) devices are capable of reversibly changing their optical properties upon charge injection and extraction induced by the external voltage. The characteristics of the EC device, such as low power consumption, high coloration efficiency, and memory effects under open circuit status, make them suitable for use in a variety of applications including smart windows and electronic papers. Coloration due to reduction or oxidation of redox chromophores can be used for EC devices (e-paper), but the switching time is slow (second level). Recently, with increasing demand for the low cost, lightweight flat panel display with paper-like readability (electronic paper), an EC display technology based on dye-modified $TiO_2$ nanoparticle electrode was developed. A well known organic dye molecule, viologen, was adsorbed on the surface of a mesoporous $TiO_2$ nanoparticle film to form the EC electrode. On the other hand, ZnO is a wide bandgap II-VI semiconductor which has been applied in many fields such as UV lasers, field effect transistors and transparent conductors. The bandgap of the bulk ZnO is about 3.37 eV, which is close to that of the $TiO_2$ (3.4 eV). As a traditional transparent conductor, ZnO has excellent electron transport properties, even in ZnO nanoparticle films. In the past few years, one-dimension (1D) nanostructures of ZnO have attracted extensive research interest. In particular, 1D ZnO nanowires renders much better electron transportation capability by providing a direct conduction path for electron transport and greatly reducing the number of grain boundaries. These unique advantages make ZnO nanowires a promising matrix electrode for EC dye molecule loading. ZnO nanowires grow vertically from the substrate and form a dense array (Fig. 1). The ZnO nanowires show regular hexagonal cross section and the average diameter of the ZnO nanowires is about 100 nm. The cross-section image of the ZnO nanowires array (Fig. 1) indicates that the length of the ZnO nanowires is about $6\;{\mu}m$. From one on/off cycle of the ZnO EC cell (Fig. 2). We can see that, the switching time of a ZnO nanowire electrode EC cell with an active area of $1\;{\times}\;1\;cm^2$ is 170 ms and 142 ms for coloration and bleaching, respectively. The coloration and bleaching time is faster compared to the $TiO_2$ mesoporous EC devices with both coloration and bleaching time of about 250 ms for a device with an active area of $2.5\;cm^2$. With further optimization, it is possible that the response time can reach ten(s) of millisecond, i.e. capable of displaying video. Fig. 3 shows a prototype with two different transmittance states. It can be seen that good contrast was obtained. The retention was at least a few hours for these prototypes. Being an oxide, ZnO is oxidation resistant, i.e. it is more durable for field emission cathode. ZnO nanotetropods were also applied to realize the first prototype triode field emission device, making use of scattered surface-conduction electrons for field emission (Fig. 4). The device has a high efficiency (field emitted electron to total electron ratio) of about 60%. With this high efficiency, we were able to fabricate some prototype displays (Fig. 5 showing some alphanumerical symbols). ZnO tetrapods have four legs, which guarantees that there is one leg always pointing upward, even using screen printing method to fabricate the cathode.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.108-109
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• 2012

This talk will begin with the demonstration of facile synthesis of silicon nanostructures using the magnesiothermic reduction on silica nanostructures prepared via self-assembly, which will be followed by the characterization results of their performance for energy storage. This talk will also report the fabrication and characterization of highly porous, stretchable, and conductive polymer nanocomposites embedded with carbon nanotubes (CNTs) for application in flexible lithium-ion batteries. It will be presented that the porous CNT-embedded PDMS nanocomposites are capable of good electrochemical performance with mechanical flexibility, suggesting these nanocomposites could be outstanding anode candidates for use in flexible lithium-ion batteries. Directed self-assembly (DSA) of block copolymers (BCPs) can generate uniform and periodic patterns within guiding templates, and has been one of the promising nanofabrication methodologies for resolving the resolution limit of optical lithography. BCP self-assembly processing is scalable and of low cost, and is well-suited for integration with existing semiconductor manufacturing techniques. This talk will introduce recent research results (of my research group) on the self-assembly of Si-containing block copolymers for the achievement of sub-10 nm resolution, fast pattern generation, transfer-printing capability onto nonplanar substrates, and device applications for nonvolatile memories. An extraordinarily facile nanofabrication approach that enables sub-10 nm resolutions through the synergic combination of nanotransfer printing (nTP) and DSA of block copolymers is also introduced. This simple printing method can be applied on oxides, metals, polymers, and non-planar substrates without pretreatments. This talk will also report the direct formation of ordered memristor nanostructures on metal and graphene electrodes by the self-assembly of Si-containing BCPs. This approach offers a practical pathway to fabricate high-density resistive memory devices without using high-cost lithography and pattern-transfer processes. Finally, this talk will present a novel approach that can relieve the power consumption issue of phase-change memories by incorporating a thin $SiO_x$ layer formed by BCP self-assembly, which locally blocks the contact between a heater electrode and a phase-change material and reduces the phase-change volume. The writing current decreases by 5 times (corresponding to a power reduction of 1/20) as the occupying area fraction of $SiO_x$ nanostructures varies.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.1-9
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• 2010

Three-dimensional (3-D) integration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip to form highly integrated micro-nano systems. Since CMOS device scaling has stalled, 3D integration technology allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. The potential benefits of 3D integration can vary depending on approach; increased multifunctionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. It is expected that the semiconductor industry's paradiam will be shift to a new industry-fusing technology era that will offer tremendous global opportunities for expanded use of 3D based technologies in highly integrated systems. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of IT-NT-BT systems. This paper attempts to introduce new 3D integration technologies of the chip self-assembling stacking and 3D heterogeneous opto-electronics integration for realizng the super-chip.

• Transactions on Electrical and Electronic Materials
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• v.17 no.5
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• pp.261-269
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• 2016

A high-performance transmit/receive (T/R) switch is essential for every radio-frequency (RF) device. This paper proposes a T/R switch that is designed in the CEDEC 0.13 μm complementary metal-oxide-semiconductor (CMOS) technology for 2.4 GHz ISM-band RF applications. The switch exhibits a 1 dB insertion loss, a 28.6 dB isolation, and a 35.8 dBm power-handling capacity in the transmit mode; meanwhile, for the 1.8 V/0 V control voltages, a 1.1 dB insertion loss and a 19.4 dB isolation were exhibited with an extremely-low power dissipation of 377.14 μW in the receive mode. Besides, the variations of the insertion loss and the isolation of the switch for a temperature change from - 25℃ to 125℃ are 0.019 dB and 0.095 dB, respectively. To obtain a lucrative performance, an active inductor-based resonant circuit, body floating, a transistor W/L optimization, and an isolated CMOS structure were adopted for the switch design. Further, due to the avoidance of bulky inductors and capacitors, a very small chip size of 0.0207 mm² that is the lowest-ever reported chip area for this frequency band was achieved.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.