• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.678-681
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• 2009

A single-pixel photon counter is designed using a folded cascode CMOS operational amplifier which is self-biased. Since there is no need for a voltage bias circuit, the layout area and power consumption of the designed counter are reduced. The signal voltage of the designed charge sensitive amplifier (CSA) with the MagnaChip $0.18{\mu}m$ CMOS process is simulated to be 138mv, near the theoretical voltage of 151mV. And the layout area of the designed counter is $100{\mu}m{\times}100{\mu}m$.

• Journal of the Optical Society of Korea
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• v.12 no.4
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• pp.232-239
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• 2008

We investigated how the polarization-mode dispersion (PMD) tolerance was degraded by semiconductor optical amplifier (SOA)-induced chirp for the 10 Gb/s nonreturn-to-zero (NRZ), duobinary NRZ, return-to-zero (RZ), and carrier-suppressed RZ (CS-RZ) modulation formats. The power penalty was calculated as a measure of the system performance due to PMD for a given SOA-induced chirp. Considering only first-order PMD, all modulation formats have a similar PMD tolerance regardless of SOA-induced chirp. On the other hand, when both first- and second-order PMD are considered, the PMD tolerance of all modulation formats with the exception of the CS-RZ modulation format are degraded by SOA-induced chirp. Among all modulation formats considered here, the NRZ modulation format has the PMD tolerance with the highest sensitivity to SOA-induced chirp. When the peak-to-peak chirp induced by SOAs is $0.28{\AA}$, its PMD tolerance is degraded up to 4 dB for a differential group delay (DGD) of 50 ps. However, the PMD tolerance of the CS-RZ modulation format is largely unaffected by SOA-induced chirp.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.1
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• pp.33-41
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• 2019

We propose an embedded solution to design a high-speed and high-accuracy 16bit analog-digital signal processing interface for the control systems using various external analog signals. Choosing TMS320F28377D micro controller unit (MCU) featuring high-performance processing in the 32-bit floating point operation, low power consumption, and various I/O device supports, we design and build the proposed system that supports both 16-bit analog-digital converter (ADC) interface and high precision digital-analog converter (DAC) interface. The ADC receives voltage-level differential signals from fully differential amplifiers, and the DAC communicates with MCU through 50 MHz bandwidth high-fast serial peripheral interface (SPI). We port the boot loader and device drivers to the implemented board, and construct the firmware development environment for the application programming. The performance of the entire implemented system is demonstrated by analog-digital signal processing tests, and is verified by comparing the test results with those of existing similar systems.

• ETRI Journal
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• v.40 no.6
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• pp.693-698
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• 2018

This paper presents a true-time delay (TTD) using a commercial $0.13-{\mu}m$ CMOS process for wideband phased-array antennas without the beam squint. The proposed TTD consists of four wideband distributed gain amplifiers (WDGAs), a 7-bit TTD circuit, and a 6-bit digital step attenuator (DSA) circuit. The T-type attenuator with a low-pass filter and the WDGAs are implemented for a low insertion loss error between the reference and time-delay states, and has a flat gain performance. The overall gain and return losses are >7 dB and >10 dB, respectively, at 2 GHz-18 GHz. The maximum time delay of 198 ps with a 1.56-ps step and the maximum attenuation of 31.5 dB with a 0.5-dB step are achieved at 2 GHz-18 GHz. The RMS time-delay and amplitude errors are <3 ps and <1 dB, respectively, at 2 GHz-18 GHz. An output P1 dB of <-0.5 dBm is achieved at 2 GHz-18 GHz. The chip size is $3.3{\times}1.6mm^2$, including pads, and the DC power consumption is 370 mW for a 3.3-V supply voltage.

• Journal of Semiconductor Engineering
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• v.2 no.1
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• pp.109-118
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• 2021

This review paper describes the overall operating principle of a discrete-time delta-sigma modulator (DTDSM) and a continuous-time delta-sigma modulator (CTDSM) using a switched-capacitor (SC). In addition, research that has solved the problems related to each delta-sigma modulator (DSM) is introduced, and the latest developments are explained. This paper describes the chopper-stabilization technique that mitigates flicker noise, which is crucial for the DSM. In the case of DTDSM, this paper addresses the problems that arise when using SC circuits and explains the importance of the operational transconductance amplifier performance of the first integrator of the DSM. In the case of CTDSM, research that has reduced power consumption, and addresses the problems of clock jitter and excess loop delay is described. The recent developments of the analog front end, which have become important due to the increasing use of wireless sensors, is also described. In addition, this paper presents the advantages and disadvantages of the three-opamp instrumentation amplifier (IA), current feedback IA (CFIA), resistive feedback IA, and capacitively coupled IA (CCIA) methods for implementing instrumentation amplifiers in AFEs.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.3
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• pp.227-247
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• 2015

An X-band $8{\times}16$ dual-polarized active phased array antenna system has been implemented based on the substrate integrated waveguide(SIW) technology having low propagation loss, complete EM shielding, and high power handling characteristics. Compared with the microstrip case, 1 dB less is the measured insertion loss(0.65 dB) of the 16-way SIW power distribution network and doubled(3 dB improved) is the measured radiation efficiency(73 %) of the SIW sub-array($1{\times}16$) antenna element. These significant improvements of the power division loss and the radiation efficiency using the SIW, save more than 30 % of the total power consumption, in the active phased array antenna systems, through substantial reduction of the maximum output power(P1 dB) of the high power amplifiers. Using the X-band $8{\times}16$ dual-polarized active phased array antenna system fabricated by the SIW technology, the main radiation beam has been steered by 0, 5, 9, and 18 degrees in the accuracy of 2 degree maximum deviation by simply generating the theoretical control vectors. Performing thermal cycle and vacuum tests, we have found that the SIW array antenna system be eligible for the space environment qualification. We expect that the high efficiency SIW array antenna system be very effective for high performance radar systems, massive MIMO for 5G mobile systems, and various millimeter-wave systems(60 GHz WPAN, 77 GHz automotive radars, high speed digital transmission systems).

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.2
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• pp.9-17
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• 2010

Recently, there has been much interest in orthogonal frequency division multiplexing (OFDM) for next generation wireless wideband communication systems. OFDM is a special case of multicarrier transmission, where a single data stream is transmitted over a number of lower-rate subcarriers. One of the main reasons to use OFDM is to increase robustness against frequency-selective fading or narrowband interference. However, in the radio systems it is also important to distortion introduced by high power amplifiers (HPA's) such as solid state power amplifier (SSPA) considered in this paper. Since the signal amplitude of the OFDM system is Rayleigh-distributed, the performance of the OFDM system is significantly degraded by the nonlinearity of the HPA in the OFDM transmitter. In this paper, we propose a canonical piecewise-linear (PWL) model based digital predistorter to prevent signal distortion and spectral re-growth due to the high peak-to-average power ratio (PAPR) of OFDM signal and the nonlinearity of HPA's. Computer simulation on an OFDM system under additive white Gaussian noise (AWGN) channels with QPSK, 16-QAM and 64-QAM modulation schemes and modulator/demodulator implemented with 1024-point FFT/IFFT, demonstrate that the proposed predistorter achieves significant performance improvement by effectively compensating for the nonlinearity introduced by the SSPA.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.381-391
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• 2010

In this paper, a novel frequency reconfigurable active array antenna(RAA) system, which can be reconfigurable for three reconfigurable frequency bands, is proposed by using commercial RF MEMS switches. The MEMS switch shows excellent insertion loss, linearity, as well as isolation. So, the system performance degradation of the reconfigurable system by using MEMS switches can be minimized. The proposed frequency reconfigurable active antenna system is consisted with the noble frequency reconfigurable front-end amplifiers(RFA) with the simple reconfigurable impedance matching circuits(RMC), reconfigurable antenna elements(RAE), as well as a reconfiguration control board(RCB) for MEMS switch control. The proposed RAA system can be reconfigurable for three frequency bands, 850 MHz, 1.9 GHz, and 3.4 GHz, with $2{\times}2$ array of the RAE having broadband printed dipole antenna topology. The validity of the proposed RFA as well as RAA is also presented with the experimental results of the fabricated systems.

• Journal of the Korea Convergence Society
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• v.7 no.3
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• pp.77-85
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• 2016

We propose a digital signal processing technic that can compensate the non-linearity inherent in audio amplifiers, and present the result of the simulation. The inherent non-linearity of the audio power amplifier arising from analog devices is compensated via a digital signal processing technic consisting of indirect learning architecture and an adaptive filter. The simulation results show that the compensator can be realized using a third-order polynomial and compensates odd-order non-linearity efficiently. The even-oder non-linearity is mainly due to the dc offset at the output, which is difficult to eliminate with the proposed method. Care must be taken in designing the bias circuit to avoid the DC offset at the output. The proposed technic has significance in that digital signal processing technic can compensate for the impairment that is an inherent characteristic of an analog system.

• Smart Media Journal
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• v.4 no.2
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• pp.55-61
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• 2015

A bandwidth-enhanced ultra-wide band (UWB) CMOS balun-LNA is implemented as a part of a software defined radio (SDR) receiver which supports multi-band and multi-standard. The proposed balun-LNA is composed of a single-to-differential converter, a differential-to-single voltage summer with inductive shunt peaking, a negative feedback network, and a differential output buffer with composite common-drain (CD) and common-source (CS) amplifiers. By feeding the single-ended output of the voltage summer to the input of the LNA through a feedback network, a wideband balun-LNA exploiting negative feedback is implemented. By adopting a source follower-based inductive shunt peaking, the proposed balun-LNA achieves a wider gain bandwidth. Two LNA design examples are presented to demonstrate the usefulness of the proposed approach. The LNA I adopts the CS amplifier with a common gate common source (CGCS) balun load as the S-to-D converter for high gain and low noise figure (NF) and the LNA II uses the differential amplifier with the ac-grounded second input terminal as the S-to-D converter for high second-order input-referred intercept point (IIP2). The 3 dB gain bandwidth of the proposed balun-LNA (LNA I) is above 5 GHz and the NF is below 4 dB from 100 MHz to 5 GHz. An average power gain of 18 dB and an IIP3 of -8 ~ -2 dBm are obtained. In simulation, IIP2 of the LNA II is at least 5 dB higher than that of the LNA I with same power consumption.