• Journal of the Korean Crystal Growth and Crystal Technology
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• v.23 no.6
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• pp.309-313
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• 2013

Silicon carbide (SiC) has recently drawn an enormous industrial interest because of its useful mechanical properties such as thermal resistance, abrasion resistance and thermal conductivity at high temperature. Especially, high purity SiC is applicable to the fields of power semiconductor and lighting emitting diode (LED). In this work, high purity carbon powders as raw material for high purity SiC were prepared by a RF induction thermal plasma. Dodecane ($C_{12}H_{26}$) as hydrocarbon liquid precursor has been utilized for synthesis of high purity carbon powders. It is found that the filtercollected carbon powders showed smaller particle size (10~20 nm) and low crystallinity compared to the reactor-collected carbon powders. The purities of reactor-collected and filter-collected carbon powders were 99.9997 % (5N7) and 99.9993 % (5N3), respectively. In addition, the impurities of carbon powders synthesized by RF induction thermal plasma were mainly originated from the surrounding environment.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.84-93
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• 2001

An electromagnetic micro x-y stage for probe-based data storage (PDS) has been fabricated. The x-y stage consists of a silicon body inside which planar copper coils are embedded, a glass substrate bonded to the silicon body, and eight permanent magnets. The dimensions of flexures and copper coils were determined to yield $100{\;}\mu\textrm{m}$ in x and y directions under 50 mA of supplied current and to have 440 Hz of natural frequency. For the application to PDS devices, electromagnetic stage should have flat top surface for the prevention of its interference with multi-probe array, and have coils with low resistance for low power consumption. In order to satisfy these design criteria, conducting planar copper coils have been electroplated within silicon trenches which have high aspect ratio ($5{\;}\mu\textrm{m}$in width and $30{\;}\mu\textrm{m}$in depth). Silicon flexures with a height of $250{\;}\mu\textrm{m}$ were fabricated by using inductively coupled plasma reactive ion etching (ICP-RIE). The characteristics of a fabricated electromagnetic stage were measured by using laser doppler vibrometer (LDV) and dynamic signal analyzer (DSA). The DC gain was $0.16{\;}\mu\textrm{m}/mA$ and the maximum displacement was $42{\;}\mu\textrm{m}$ at a current of 180 mA. The measured natural frequency of the lowest mode was 325 Hz. Compared with the designed values, the lower natural frequency and DC gain of the fabricated device are due to the reverse-tapered ICP-RIE process and the incomplete assembly of the upper-sided permanent magnets for LDV measurements.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.411-424
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• 2017

An all-digital delay-locked loop (DLL) for a mobile memory interface, which runs at 0.11-2.5 GHz with a phase-shift capability of $180^{\circ}$, has two internal DLLs: a global DLL which uses a time-to-digital converter to assist fast locking, and shuts down after locking to save power; and a local DLL which uses a phase detector with an adaptive phase sampling window (WPD) to reduce jitter accumulation. The WPD in the local DLL adjusts the width of its sampling window adaptively to control the loop bandwidth, thus reducing jitter induced by UP/DN dithering, input clock jitter, and supply/ground noise. Implemented in a 65 nm CMOS process, the DLL operates over 0.11-2.5 GHz. It locks within 6 clock cycles at 0.11 GHz, and within 17 clock cycles at 2.5 GHz. At 2.5 GHz, the integrated jitter is $954fs_{rms}$, and the long-term jitter is $2.33ps_{rms}/23.10ps_{pp}$. The ratio of the RMS jitter at the output to that at the input is about 1.17 at 2.5 GHz, when the sampling window of the WPD is being adjusted adaptively. The DLL consumes 1.77 mW/GHz and occupies $0.075mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.658-665
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• 2014

The neural stimulators have been employed to the visual prostheses system based on the functional electrical stimulation (FES). Due to the size limitation of the implantable device, the smaller area of the unit current driver pixel is highly desired for higher resolution current stimulation system. This paper presents a 16-channel compact current-mode neural stimulator IC with digital to analog converter (DAC) sharing scheme for artificial retinal prostheses. The individual pixel circuits in the stimulator IC share a single 6 bit DAC using the sample-and-hold scheme. The DAC sharing scheme enables the simultaneous stimulation on multiple active pixels with a single DAC while maintaining small size and low power. The layout size of the stimulator circuit with the DAC sharing scheme is reduced to be 51.98 %, compared to the conventional scheme. The stimulator IC is designed using standard $0.18{\mu}m$ 1P6M process. The chip size except the I/O cells is $437{\mu}m{\times}501{\mu}m$.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.136.2-136.2
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• 2015

반도체 제조는 chip의 성능 향상 및 단가 하락을 위해 지속적으로 pattern size가 nano size로 감소해 왔고, capacitor 용량은 증가해 왔다. 이러한 현상은 contact hole의 aspect ratio를 지속적으로 증가시킨바, 그에 따라 최적의 HARC (high aspect ratio contact)을 확보하는 적합한 dry etch process가 필수적이다. 그러나 HARC dry etch process는 많은 critical plasma properties 에 의존하는 매우 복잡한 공정이다. 따라서, critical plasma properties를 적절히 조절하여 higher aspect ratio, higher etch selectivity, tighter critical dimension control, lower P2ID과 같은 plasma characteristics을 확보하는 것이 요구된다. 현재 critical plasma properties를 제어하기 위해 다양한 plasma etching 방법이 연구 되어왔다. 이 중 plasma를 낮은 kHz의 frequency에서 on/off 하는 pulsed plasma etching technique은 nanoscale semiconductor material의 etch 특성을 효과적으로 향상 시킬 수 있다. 따라서 본 실험에서는 dual-frequency capacitive coupled plasma (DF-CCP)을 사용하여 plasma operation 동안 duty ratio와 pulse frequency와 같은 pulse parameters를 적용하여 plasma의 특성을 각각 제어함으로써 etch selectivity와 uniformity를 향상 시키고자 하였다. Selective SiO2 contact etching을 위해 top electrode에는 60 MHz pulsed RF source power를, bottom electrode에는 2MHz pulse plasma를 인가하여 synchronously pulsed dual-frequency capacitive coupled plasma (DF-CCP)에서의 plasma 특성과 dual pulsed plasma의 sync. pulsing duty ratio의 영향에 따른 etching 특성 등을 연구 진행하였다. 또한 emissive probe를 통해 전자온도, OES를 통한 radical 분석으로 critical Plasma properties를 분석하였고 SEM을 통한 etch 특성분석과 XPS를 통한 표면분석도 함께 진행하였다. 그 결과 60%의 source duty percentage와 50%의 bias duty percentage에서 가장 향상된 etch 특성을 얻을 수 있었다.

• Tribology and Lubricants
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• v.33 no.3
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• pp.106-111
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• 2017

Sapphire is an anisotropic material with excellent physical and chemical properties and is used as a substrate material in various fields such as LED (light emitting diode), power semiconductor, superconductor, sensor, and optical devices. Sapphire is processed into the final substrate through multi-wire saw, double-side lapping, heat treatment, diamond mechanical polishing, and chemical mechanical polishing. Among these, chemical mechanical polishing is the key process that determines the final surface quality of the substrate. Recent studies have reported that the material removal characteristics during chemical mechanical polishing changes according to the crystal orientations, however, detailed analysis of this phenomenon has not reported. In this work, we carried out chemical mechanical polishing of C(0001), R($1{\bar{1}}02$), and A($11{\bar{2}}0$) substrates with different sapphire crystal planes, and analyzed the effect of crystal orientation on the material removal characteristics and their correlations. We measured the material removal rate and frictional force to determine the material removal phenomenon, and performed nano-indentation to evaluate the material characteristics before and after the reaction. Our findings show that the material removal rate and frictional force depend on the crystal orientation, and the chemical reaction between the sapphire substrate and the slurry accelerates the material removal rate during chemical mechanical polishing.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.8
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• pp.883-890
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• 2015

As the semiconductor processing technology has been developing, multiple cores or NoC(network on chip) can be contained in recent chips. GALS(globally asychronous locally synchronous) clocking scheme that has multi-clock domains with different frequencies or phase differences is widely used to solve power consumption and clock skew in a large chip with a single clock. A synchronizer is needed to avoid a synchronization problem between sender and receiver in GALS. In this paper, the setup and hold time of DFF required to design the synchronizer are measured using 180nm CMOS processing parameters depending on temperature, supply voltage, and the size of inverter in DFF. The simulation results based on the bisection method in HSPICE show that the setup and hold time are proportional to temperature, however they are inversely proportional to supply voltage, and negative values are measured for the hold time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.4
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• pp.877-887
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• 2015

In this paper, a design of communication joint tools to implement a legacy-line communication (LLC) system, which exploits various conductive lines in a train, is presented. We develop two kinds of joint tools; one is a conductive joint tool (CJT) that is connected directly to the conventional lines and the other is the inductive joint tool (IJT) which connects the conventional lines indirectly using electromagnetic induction. As a result, the practical experiment of data communication confirms that an LLC system with the developed joint tools has a transmission rate more than 20 Mbps in the distance of 200 m away. In addition, an environmental durability test shows that the joint tools operate stably in an extreme environmenal variation. It is, therefore, considered that the developed joint tools are very useful to implement a communication network in the train working currently.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.40 no.2
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• pp.213-220
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• 2016

This research aims to develop core technologies for passive carrier (no power in carrier itself) transfer system. The technologies are passive levitation, propulsion, and guidance, which can be great benefits for semiconductor and display manufacturing industries. Passive maglev carrier is necessary to precise position control for quiet and stable transfer operation. However, the structural characteristics of carrier and the installation errors of gap sensors cause the pitch motion. Hence, the controller design in consideration of pitch motion is required. This study deals with the reduction control of carrier pitch motion. PDA controller and PDA controller with pitch control are proposed to compare the pitch angle analysis. The pitch angle and the levitation precision are measured by experiment. Finally, the optimized design of pitch controller is presented and the effects are discussed.

• Journal of Sensor Science and Technology
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• v.23 no.5
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• pp.332-336
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• 2014

In this paper, we propose a complementary metal oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) PMOSFET-type photodetector for high-speed operation. The GBT photodetector of an active pixel sensor (APS) consists of a floating gate ($n^+$-polysilicon) tied to the body (n-well) of the PMOSFET. The p-n junction photodiode that is used in a conventional APS has a good dynamic range but low photosensitivity. On the other hand, a high-gain GBT photodetector has a high level of photosensitivity but a narrow dynamic range. In addition, the pixel size of the GBT photodetector APS is less than that of the conventional photodiode APS because of its use of a PMOSFET-type photodetector, enabling increased image resolution. A CMOS binary image sensor can be designed with simple circuits, as a complex analog to digital converter (ADC) is not required for binary processing. Because of this feature, the binary image sensor has low power consumption and high speed, with the ability to switch back and forth between a binary mode and an analog mode. The proposed CMOS binary image sensor was simulated and designed using a standard CMOS $0.18{\mu}m$ process.