• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.296-299
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• 2004

This paper introduces a supplementary module reducing tile standby-power of Power Line Communication(PLC) modem, one of the network equipments that take up much of tile stand-by power. This supplementary module consists of three parts, such as a compare part, a control part, and a switch part. This supplementary module controls the power going from the power supply element into PLC modem, which brings about the effect of standby-power reduction. It is assured that over 30% standby-power reduction is estimated when we applied this module to a low-speedy PLC control modem.

• Proceedings of the KIEE Conference
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• 2002.11d
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• pp.369-371
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• 2002

The railway power feeding system is divided into AC power feeding system and DC power feeding system. In downtown area. DC power feeding system is used and AC power feeding system is used in intercity railway system. AC power feeding system raises a inductive disturbance that is divided into electrostatic induction and electromagnetic induction. Especially, it has a bad effect on communication lines. So inductive disturbance reduction method has been adopted in many system. In this paper, we deals with the inductive disturbance reduction method of railway power feeding system and of sides affected by inductive disturbance.

• International Journal of Aeronautical and Space Sciences
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• v.2 no.2
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• pp.19-27
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• 2001

This research attempts to find an active control strategy which reduces acoustic power and acoustic energy in lightly-damped enclosed sound field such as a vehicle compartment or an operating room of heavy industrial machinery. An active control strategy, which takes into consideration of the acoustic radiation power of the source as a cost function, is formulated and examined to find capability of reducing noise. An adaptive filtering algorithm for sound power control is suggested and implemented to control lightly-damped sound field. To verify the method, sound power based active noise control algorithm was implemented on a rectangular box with lightly-damped wall, and popular acoustic energy based control with modal coupling reduction was performed to compare the noise reduction performance. It was shown that a total sound power based strategy provides a practical mean for global noise reduction for lightly damped sound field.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.402-403
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• 2009

A variety of power reduction technologies is introduced and the benefits of the technologies are discussed. PenTile$^{(R)}$ DBLC (Dynamic Brightness LED Control) combined with SABC (Sensor-Based Adaptive Brightness Control) enables to achieve the average LED power consumption to one third. The panel power reduction of 25% can be achieved with low power driving technology, ALS (Active Level Shifter). MIP (Memory In Pixel) is expected to be useful in transflective display because the whole display area can be utilized in reflective mode with power consumption of 1mW.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.2
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• pp.91-99
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• 2015

The electric power consumed by the embedded devices has become a critical issue because the reduction of power consumption is an important factor to prolong the battery-operated devices' lifetime. Many researches and techniques to reduce the power consumption have been proposed and developed but any power method cannot guarantee optimal power consumption of an embedded device - it would be faced with numerous situation - in all ways. Specifically, power researches for embedded devices deployed in the industry field have hardly been done. In this paper, low power service is proposed to minimize power reduction with the several usage status of embedded devices in the industry field. The usage status is basically classified according to the distance between the device and the user which is obtained by the ultrasonic and PIR sensor. The performance evaluation shows that the proposed scheme can reduce the power consumption by up to 45.3% compared to the device with no power reduction scheme. It also shows that the power consumption of the proposed scheme is 5.2% ~ 16.8% lower than that of the timeout scheme.

• KEPCO Journal on Electric Power and Energy
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• v.5 no.4
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• pp.331-335
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• 2019

In this study we investigate catalytic activity and selectivity of mixture of Ag and ketjenblack according to their ratios by product analysis and electrochemical experiments, such as cyclic voltammetry, linear sweep voltammetry and chronoamperometry. We reveal that catalytic activity toward CO₂ reduction to CO is improved by simple mixing Ag nanoparticle and ketjenblack because addition of ketjenblack suppresses aggregation of Ag nanoparticles and brings increase in electrochemical active surface area. However, excess amount of ketjenblack rather inhibit the CO₂ reduction to CO. These observations provide clues to develop highly active Ag catalyst or electrode toward electrochemical reduction of CO₂.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.10
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• pp.1902-1910
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• 2009

This paper presents a graphical windows-based program for the education and training for novel network reduction. The object of developed simulator is to provide users with a simple and useable tool for gaining an intuitive feel for power system analysis. The developed simulator consists of the main module (MMI,GUI), the location marginal price module (LMP), the clustering module and network reduction module. Each module has a separate graphical and interactive interfacing window. The developed simulator needs with the PSS/E input data format, generator cost function, location information. Line admittances of reduced network was determined by using the power flow method(Newton-Raphson). So line flow of reduced network is almost same to original power system. Results of reduced network are compared on the window in the tabular format. Therefore, the developed simulator can be utilized as a useful tool for effective education and training for power system analysis.

• Proceedings of the KIEE Conference
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• 2005.10c
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• pp.122-125
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• 2005

A novel torque ripple reduction scheme of single-phase SRM with high power factor is presented. The proposed SRM drive has one additional active switches in the conventional asymmetric inverter. In order to get a higher power factor, the source current is controlled sinusoidal, And additional excitation current is added from charge capacitor due to torque ripple reduction. The switching period of source and charged voltage is controlled properly to get unity power factor and torque ripple reduction. The characteristics and validity of the proposed scheme is discussed with some simulation results.

• The Magazine of the IEIE
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• v.25 no.5
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• pp.31-41
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• 1998

With the advent of portable electronic systems, power consumption has recently become a major issue in circuit and system design. Furthermore, the sophisticated fabrication technology makes it possible to embed more functions and features in a VLSI chip, consequently calling for both higher performance and lower power to deal with the ever growing complexity of system algorithms than in the past. VLSI designers should cope with two conflicting constraints, high performance and low power, offering an optimum trade off of these constraints to meet requirements of system. Historically, VLSI designers have focused on performance improvement, and power dissipation was not a design criteria but an afterthought. This design paradigm should be changed, as power is emerging as the most critical design constraint. In VLSI design, low power design can be accomplished through many ways, for instance, process, circuit/logic design, architectural design, and etc.. In this paper, a few low power design examples, which have been used in 8 bit micro-controller core, and can be used also in 4/16/32 bit micro-controller cores, are presented in the areas of circuit, logic and architectural design. We first propose a low power guidelines for micro-controller design in SAMSUNG, and more detailed design examples are followed applying 4 specific design guidelines. The 1st example shows the power reduction through reduction of number of state clocks per instruction. The 2nd example realized the power reduction by applying RISC(Reduced Instruction Set Computer) concept. The 3rd example is to optimize the algorithm for ALU(Arithmetic Logic Unit) to lower the power consumption, Lastly, circuit cells designed for low power are described.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.66 no.1
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• pp.7-14
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• 2017

Recently, the power consumption of industrial consumer has increased rapidly, causing problems such as lack of power reserve margin in summer and winter, and therefore there is a growing need for maximum demand power management to consumers. In this paper, we studied small microgrid system consisting of battery ESS and photovoltaic power system, applied to small and medium sized factories to reduce the maximum demand power of daily industrial power load. To verify the validity of the study, we simulated a small microgrid system using Matlab/Simulink software. As a result of applying the simulation to small and medium sized plants that consume a lot of power, it is confirmed that there is a 13% reduction in demand compared to the existing maximum demand power. This result is expected to contribute to the improvement of the power reserve margin.