• Journal of the Korea Safety Management & Science
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• v.24 no.2
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• pp.1-9
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• 2022

In korea, 500MW standard coal fired power plants were designed and operated for the initial base load, so facility stability was prioritized from facility problem to treatment, but now we needed to research for minimizing greehouse gas emissions at the operation of coal fired power plants. research on various facilities and technologies was actively conducted to reduce environment pollutants was drastically reduced, but research and attempts on coping measures in the event of a reduction facility problem were in sufficient. this study considered investigated ways to minimized pollutants by quickly responding to logic development and application of the load runback concept in case of serious problems with environmental pollutant reduction facilities such as NOx reduction selective catalytic reduction facilities, SOx reduction wet flue gas desulpherisation facilities, and TSP(Total Suspended Particles) collection low temperature electric precipitator.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.101-104
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• 2002

This paper propose that is algorithm of power dissipation reduction in the high level synthesis design for DSP(Digital Signal Processor), as the portable terminal system recently demand high power dissipation. This paper obtain effect of power dissipation reduction and switching activity that increase correlation of operands as input data of function unit. The algorithm search loop or repeatedly data to the input operands of function unit. That can be reduce the power dissipation using the new low power high level synthesis algorithm. In this Paper, scheduling operation search same nodes from input DFG(Data Flow Graph) with correlation coefficient of first input node and among nodes. Function units consist a multiplier, an adder and a register. The power estimation method is added switching activity for each bits of nodes. The power estimation have good efficient using proposed algorithm. This paper result obtain more Power reduction of fifty percents after using a new low power algorithm in a function unit as multiplier.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1058-1061
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• 2002

This paper presents the method of low power optimization considering the glitch reduction in CMOS circuits. Our algorithm utilizes the information of MOS size, the load capacitance of fan-out, and input slew to calculate the output waveform by using the linear signal model. Therefore, the accurate waveform of glitch can be obtained for estimation of power dissipation caused by glitches. Our algorithm is applied to ISCAS’85 benchmark circuits and experimental results show 23% glitch reduction and 11% total power reduction.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.12 no.3
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• pp.251-257
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• 2000

District heating and cooling systems offer highly efficient energy utilization and maintenance by centralizing heat management. More pumping power, however, is required because the water has to travel long distance from heat source to the users. In the present study, a trace of drag reduction additives is added to the District Cooling system to achieve a significant drag reduction and save pumping power. Water-soluble polymers, surfactants, and environment-friendly degradable polymers are used as effective drag reducing additives. Time dependent percent drag reductions are compared for various additive solutions at 100 wppm concentration for different water velocity. Without as an anionic surfactant, copolymer was most effective in percent drag reduction. It is found that there exists an optimal condition when copolymer is mixed with SDS. An environment-friendly degradable polymer, xanthan gum, is found to be a significant drag reduction additive. Ice slurry systems, can give less pressure drops compared with chilled water system for certain condtions. Drag reduction additives were also effective for the ice slurry system.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.2
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• pp.117-126
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• 2011

RSA-CRT algorithm is widely used to improve the performance of RSA algorithm. However, it is also vulnerable to side channel attacks like as general RSA. One of the power attacks on RSA-CRT, proposed by Boer et al., is a power analysis which utilizes reduction steps of RSA-CRT algorithm with equidistant chosen messages, called as ECMPA(Equidistant Chosen Messages Power Analysis) or MRED(Modular Reduction on Equidistant Data) analysis. This method is to find reduction output value r=xmodp which has the same equidistant patterns as equidistant messages. One can easily compute secret prime p from exposure of r. However, the result of analysis from a reduction step in [5] is remarkably different in our experiment from what Boer expected in [5]. Especially, we found that there are Ghost key patterns depending on the selection of attack bits and selected reduction algorithms. Thus, in this paper we propose several Ghost key patterns unknown to us until now, then we suggest enhanced and detailed analyzing methods.

• Proceedings of the KIEE Conference
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• 1987.11a
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• pp.359-361
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• 1987

It is known that the reactive component of AC power in the Power system gives no energy to outside and causes enlargement of power apparatus, voltage fluctuation and unstability of power system. The power conversion system and control system which are composed of power semiconductor devices such as Thyrisor, transistor, GTO and so on have been appeared as new sources of Harmonics. So the reduction of harmonics in power semiconductor system is one of impending problems on the point of energy conservation and improvement of power factor. This paper treates the fundamental review of the harmonics reduction by Current type PWM-Inverter. This Inverter-detects not only the fundamental wave but also that of all harmonics created in the power semiconductor system and is scheduled to control by sampled value.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.216-224
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• 2009

The endless scaling down of the semiconductor process made the impact of the power network noise on the performance of the state-of-the-art chip a serious design problem. This paper compares the performances of two popular circuit reduction approaches used to improve the efficiency of power network noise analysis: moment matching-based model order reduction (MOR) and node elimination-based MOR. As the benchmarks, we chose PRIMA and R2Power as the matching-based MOR and the node elimination-based MOR. Experimental results indicate that the accuracy, efficiency, and memory requirement of both methods very strongly depend on the structure of the given circuit, i.e., numbers of the nodes and sources, and the number of moments to preserve for PRIMA. PRIMA has higher accuracy in general, while the error of R2Power is also in the acceptable range. On the other hand, PRIMA has the higher efficiency than R2Power, only when the numbers of nodes and sources are small enough. Otherwise, R2Power clearly outperforms PRIMA in efficiency. In the memory requirement, the memory size of PRIMA increases very quickly as the numbers of nodes, sources, and preserved moments increase.

• Proceedings of the KIEE Conference
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• 2006.04b
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• pp.57-61
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• 2006

In the single-phase switched reluctance motor (SRM) drive, the required DC source is generally supplied by the circuit consisting of bridge rectifier and large filter capacitor connected with DC line terminal. Due to the large capacity of the capacitor, the charged time of capacitor is very short from the AC source. Lead to the bridge rectifiers draws pulsating current from the AC source side, which results in reduction of power factor and low system efficiency. Therefore a novel single-phase SRM drive system is presented in this paper, which includes drive circuit realizing reduction of torque ripple and improvement of power factor with a novel switching topology. The proposed drive circuit consists of one switching part and diode, which can separate the output of AC/DC rectifier from the large capacitor and supply power to SRM alternately, in order to realize the torque ripple reduction and power factor improvement through the switching scheme. In addition, the validity of the proposed method is tested by some simulations and experiments.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.20-27
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• 1997

In this paper, a multiplying digital-to-analog converter (MDAC) circuit for low-power high-resolution CMOS algorithmic A/D converters (ADC's) is proposed. The proposed MDAC is designed to operte properly at a supply at a supply voltge between 3 V and 5 V and employs an analog0domain power reduction technique based on a bias switching circuit so that the total power consumption can be optimized. As metal-to-metal capacitors are implemented as frequency compensation capacitors, opamps' performance can be varied by imperfect process control. The MDAC minimizes the effects by the circuit performance variations with on-chip tuning circuits. The proposed low-power MDAC is implementd as a sub-block of a 10-bit 200kHz algorithmic ADC using a 0.6 um single-poly double-metal n-well CMOS technology. With the power-reduction technique enabled, the power consumption of the experimental ADC is reduced from 11mW to 7mW at a 3.3V supply voltage and the power reduction ratio of 36% is achieved.

• Proceedings of the KIEE Conference
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• summer
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• pp.1537-1539
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• 2004

This paper introduces a supplementary module reducing the standby-power of Power Line Communication(PLC) modem, one of the network equipments that take up much of the stand-by power. This supplementary module consists of three parts, such as a compare part, a control part, and a switch part. This supplementary module controls the power going from the power supply element into PLC modem, which brings about the effect of standby-power reduction. It is assured that over $30\%$ standby-power reduction is estimated when we applied this module to a low-speedy PLC control modem.