• 한국정보전자통신기술학회논문지
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• 제11권5호
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• pp.565-571
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• 2018

본 논문은 주 블레이드를 V 형태로 설계하고 주 블레이드와 보조 블레이드의 매수를 변화시켜 최상의 설계조건을 확인하고자 한다. 출력과 효율은 주 블레이드 매수가 증가할수록 증가되었다. sample 2는 sample 1과 비교하면 출력이 50% 상승하였다. sample 3은 92.8%, sample 4는 114.2% 정도 상승하였으며, 효율은 sample 1과 비교하여 sample 2는 38.4%, sample 3과 sample 4는 각각 92.3%, 107.7% 상승하였다. 보조 블레이드 매수를 증가 할수록 출력과 효율이 증가되었다. sample 6은 sample 5와 비교하면 출력이 33.3% 증가하였고. sample 7은 42.1% 증가하였다. 효율은 sample 5와 비교하여 sample 6은 35.3%, sample 7은 47.1% 정도 증가되었다. 보조 블레이드와 주 블레이드를 각각 30매로 하였을 때(sample 8) 가장 높은 출력과 효율이 측정되었다. sample 8은 sample 4와 비교하면 출력은 5.6% 및 효율은 3.7% 증가하였다. sample 7과 비교하면 sample 8은 효율이 12% 및 출력이 17.3% 증가되었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1169-1172
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• 2003

In this paper, a CLB-based CPLD low-power technology mapping algorithm consider area and delay time is proposed. To perform low power technology mapping for CPLD, a given Boolean network have to be represented to DAG. The proposed algorithm are consist of three step. In the first step, TD(Transition Density) calculation have to be performed. In the second step, the feasible clusters are generated by considering the following conditions: the number of output, the number of input and the number of OR-terms for CLB(Common Logic Block) within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low power technology mapping based on the CLBs is packing the feasible clusters into the several proper CLBs. The proposed algorithm is examined by using benchmarks in SIS. In the case of that the number of OR-terms is 5, the experiments results show that reduce the power consumption by 30.73% comparing with that of TEMPLA, and 17.11% comparing with that of PLAmap respectively.

• Journal of Power Electronics
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• 제14권3호
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• pp.507-518
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• 2014

This paper presents a new cascaded asymmetrical single phase multilevel converter with a lower number of power semiconductor switches and isolated DC sources. Therefore, the number of power electronic devices, converter losses, size, and cost are reduced. The proposed multilevel converter topology consists of two H-bridges connected in cascaded configuration. One H-bridge operates at a high frequency (high frequency inverter) and is capable of developing a two level output while the other H-bridge operates at the fundamental frequency (low frequency inverter) and is capable of developing a multilevel output. The addition of each power electronic switch to the low frequency inverter increases the number of levels by four. This paper also introduces a hybrid switching algorithm which uses very simple arithmetic and logical operations. The simplified hybrid switching algorithm is generalized for any number of levels. The proposed simplified switching algorithm is developed using a TMS320F2812 DSP board. The operation and performance of the proposed multilevel converter are verified by simulations using MATLAB/SIMULINK and experimental results.

• Journal of Power Electronics
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• 제16권6호
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• pp.2139-2149
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• 2016

In this study, a new type of cascaded modular multilevel inverters (CMMLIs) is presented which is able to produce a considerable number of output voltage levels with a reasonable number of components. Accordingly, each series stage of the proposed CMMLI is comprised of two same basic units that are connected with each other through two unidirectional power switches without aiming any of the full H-bridge cells. In addition, since the potentiality for generating a higher number of output voltage levels in CMMLIs hinges on the magnitude of the dc voltage sources used in each series unit, in the rest of this paper, four different algorithms for determining an appropriate value for the dc sources' magnitude are also presented. In the following, a comprehensive topological analysis between some CMMLI structures reported in the literature and proposed structure along with several simulation and experimental results will be also given to validate the lucrative benefits and viability of the proposed topology.

• 대한의용생체공학회:의공학회지
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• 제22권3호
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• pp.241-247
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• 2001

ABR(auditory brainstem response) is one of the audiometry which measures objective hearing threshold level by acquiring electric evoked potentials emanated from auditory nerve system responding to an auditory stimulation. However, the obtained potentials which are largely interfered by power line noise, have extremely low SNR, thus ensemble average algorithm is generally used. The purpose of this study was to investigate the effect of iteration number in ensemble average on the reduction of the power line noise. The power line noise was modeled to be a 60 Hz sinusoidal signal and the energy of the modeled signal was calculated when it was averaged. It was verified by simulation that the energy had the periodic zero points for each stimulation rate, and 60 Hz signal induced by the power line was applied to the developed ABR system to confirm that the period of zero energy point was the same with that of the simulation. By the properly selected iteration number, power line noise could be reduced and more reliable ABR could be acquired.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
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• pp.920-927
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• 1998

This paper proposed that an Analysis of a partial resonant AC-DC converter for high power and power factor operates with four choppers connecting to a number of parallel circuit. To improve these, a large number of soft switching topologies included a resonant circuit have been proposed. And, some simulative results on computer are included to confirm the validity of the analytical results. The partial resonant circuit makes use of an inductor using step-down and a condenser of lose-less snubber. The result is that the switching loss is very low and the efficiency of system is high. And the snubber condenser used in a partial resonant circuit makes charging energy regenerated at input power source for resonant operation. The proposed conversion system is deemed the most suitable for high power applications where the power switching devices are used

• 항공우주시스템공학회지
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• 제11권6호
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• pp.50-55
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• 2017

본 논문은 란체스터 방정식을 이용하여 우리의 무인전투기(블루군)과 적 무인전투기(레드군) 간의 교전 결과를 예측하였다. 란체스터 법칙은 군단의 전력이 전투원 수에 비례한다는 제1법칙(linear law)과 전투원 수의 제곱에 비례한다는 제2법칙(square law)가 있다. 제1법칙은 게릴라전에 적합한 법칙이고 제2법칙은 전면전에 적합한 법칙으로 알려져 있으며 일반적으로 제2법칙이 많이 쓰인다. 란체스터의 제2법칙을 이용하여 교전 결과를 예측하였다. 교전에서 승리하기 위한 전투손실률 값은 물론 필요 전력수를 추산하였고, 우리 군의 피해를 1대 미만으로 만들기 위한 전력수도 예측하였다. 적 무인전투기와 아군 무인전투기의 전투 대수가 같을 경우 승리를 보장받으려면 전투손실률이 1:1.5 이상이 되어야 한다.

• ETRI Journal
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• 제33권1호
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• pp.1-5
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• 2011

Downlink transmit power allocation schemes are proposed for soft fractional frequency reuse (FFR) in loose and tightly coordinated systems. The transmit powers are allocated so that the loss of spectral efficiency from the soft FFR is minimized, and the required cell edge user throughput is guaranteed. The effect of the soft FFR on spectral efficiency is evaluated depending on the power allocation schemes and the number of subbands. Results show that the loss of spectral efficiency from the soft FFR can be reduced by configuring an appropriate number of subbands in the loosely coordinated systems. In tightly coordinated systems, results show that the loss of spectral efficiency can be minimized regardless of the number of subbands due to its fast coordination.

• Journal of Power Electronics
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• 제18권2호
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• pp.418-431
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• 2018

This paper presents a new asymmetrical multilevel inverter with a reduced number of power electronic components. The proposed multilevel inverter is analyzed using two different configurations: i) First Configuration (with a switched diode) and ii) Second Configuration (without a switched diode). The presented topologies are compared with recent multilevel inverter topologies in terms of number of switches, gate driver circuits and blocking voltages. The proposed topologies can be cascaded to generate the maximum number of output voltage levels and they are suitable for high voltage applications. Various power quality issues are addressed for both of the configurations. The proposed 11-level inverter configuration is simulated using MATLAB and it is validated with a laboratory based experimental setup.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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• pp.13-18
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• 1998

After Computer-based PD measurement was referred in the 1970's, the new technology and a number of digital system have been studied. And the selection of PD patterns, extraction of relevant information for PD recognition are discussed because the number of pulse as a function of discharge magnitude and discharge pulse as a function of the power frequency cycl4e offer the information of the aging insulation. This paper investigates the discharge phase($\phi$) and magnitude(q), as well as the number of discharge(n) with regard to discharge signals generated in power cable. Therefore, according to properties analysis on the distribution of $\phi$ , q and n, it is able to apply in the aging analysis of power cable which visual observation is impossible and distribution change of discharge signals offers much information for risk degree on aging progress of insulation materials.