• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.41-45
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• 2013

Modern electronic devices such as tablets and smartphones are getting more powerful and efficient. The demand in feature sets, functionality and usability increase exponentially and this has posed a great challenge to the design of a power distribution network (PDN). Power rails merging is a popular option used today in a PDN design as numerous power rails are no longer feasible due to form factor limitation and cost constraint. In this paper, the criteria and limitations for power rails merging are discussed. Despite having all the advantages such as pin count reduction, decoupling capacitors sharing, lower impedance and cost saving, power rails merging can however, introduce coupling noise to the system. In view of this, a PDN design with power rails merging that fulfills design recommendations and specifications such as noise target, power well placement, voltage supply values as well as power supply quadrant assignment is extremely important.

• 대한전기학회논문지:시스템및제어부문D
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• 제52권4호
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• pp.246-251
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• 2003

This paper proposes a new methodology for the estimation of impedance characteristics, which is one of the important issue in the power distribution network design of printed circuit boards. The modeling process of the proposed method divides the power distribution network into uniform segment, and each segment is modeled by distributed RLC transmission lines. Then, for the efficient computation of impedance characteristics in frequency domain. the proposed method uses a model-order reduction method.

• 대한전기학회논문지:전력기술부문A
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• 제52권3호
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• pp.151-157
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• 2003

Wind farm interconnected with grid can supply the power into a power network not only the normal conditions, but also the fault conditions of distribution network. If the fault happened in the distribution power line with wind fm, the fault current level measured in a relaying point might be lower than that of distribution network without wind turbine generator due to the contribution of wind farm. Consequently, it may be difficult to detect the fault happened in the distribution network connected with wind generator This paper describes the effect of the interconnected wind turbine generators on protective relaying of distribution power lines and detection of the fault occurred in a power line network. Simulation results shows that the current level of fault happened in the power line with wind farm depends on the fault impedance, the fault location. the output of wind farm. and the load condition of distribution network.

• 대한전자공학회논문지SD
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• 제48권7호
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• pp.76-81
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• 2011

본 논문에서는 비아 절단 구조를 제안하고 2층 구조의 DRAM 패키지 기판 설계에 적용하여 낮은 임피던스를 가지는 파워 분배망(Power Distribution Network)을 구현하였다. 제안한 신규 비아 구조는 비아의 일부가 절단된 형태이고 본딩 패드와 결합하여 넓은 배선 면적을 필요로 하지 않는 장점을 가진다. 또한 비아 절단 구조를 적용한 설계에서는 본딩 패드에서 VSSQ까지의 배선 경로를 효과적으로 단축시킴으로써 PDN 임피던스를 개선시킬 수 있다. DRAM 패키지 기판 상의 윈도우 영역 형성과 동시에 비아의 일부 영역이 제거되므로 비아 절단 구조 제작을 위한 추가적인 공정은 없다. 또한 비아 홀 내부를 솔더 레지스트로 채움으로써 버(Burr) 발생을 최소화하였으며, 이를 패키지 기판 단면 촬영을 통해 검증하였다. 비아 절단 구조의 적용 및 VDDQ/VSSQ 배치에 의한 PDN 임피던스 변화를 검증하기 위해서 3차원 전자장 시뮬레이션 및 네트워크 분석기 측정을 통해 기존 방식을 적용한 패키지 기판과 비교 검증을 진행하였다. 신규 DRAM 패키지 기판은 대부분의 주파수 범위에서 보다 우수한 PDN 임피던스를 가졌으며, 이는 제안한 비아 절단 구조와 파워/그라운드 설계 배치가 PDN 임피던스 감소에 효과적임을 증명한다.

• 마이크로전자및패키징학회지
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• 제13권4호
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• pp.9-15
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• 2006

이 논문은 코어와 I/O 회로가 포함된 PEEC(Partial Equivalent Electrical Circuit) PDN(Power Distribution Networks)의 임피던스 변화에 따른 칩의 성능 분석을 나타내었다. I/O 전원에 연결된 코어 전원 잡음이 I/O 스위칭에 어떠한 영향이 미치는지 시뮬레이션 결과를 통하여 보였다. 또한 직접 설계한 $7{\times}5$인치 DLL(Delay Locked Loop)시험 보드를 사용하여 칩의 동작 지점에 따른 전원 잡음의 효과를 분석하였다. $50{\sim}400MHz$에 주파수 대역에 따른 DLL의 지터를 측정하고 시뮬레이션 결과로 얻어진 임피던스 값과 비교하였다. PDN의 공진 피크가 100MHz 주파수에서 1옴보다 큰 임피던스를 갖기 때문에 DLL의 지터는 주파수가 100MHz 근처에서 증가함을 보여준다. 타겟 임피던스를 줄이기 위한 방법인 디커플링 커패시터에 따른 칩과 보드의 임피던스 변화를 보였다. 따라서 전원 공급망 설계는 디커플링 커패시터와 함께 코어 스위칭 전류와 I/O 스위칭 전류를 같이 고려해야 한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 추계학술대회 논문집 학회본부
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• pp.405-407
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• 1994

In order to provide reliable power service and to prevent a potentail hazard and damage, it is important to detect high impedance fault in power distribution line. This paper presents a neural network based approach for the detection of high impedance faults. A time delay neural network has been selected and trained for the fault currents obtained from field experiments. Detection experiments have been performed with the data from four different high impedance surfaces. Experimental results indicated the feasibility of using TDNN for the detection of high impedance faults.

• 대한전기학회논문지:전력기술부문A
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• 제50권3호
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• pp.105-111
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• 2001

The research presented in this paper focuses on a method for the detection of High Impedance Fault(HIF). The method will use the wavelet transform and neural network system. HIF on the multi-grounded three-phase four-wires primary distribution power system cannot be detected effectively by existing over current sensing devices. These paper describes the application of discrete wavelet transform to the various HIF data. These data were measured in actual 22-9kV distribution system. Wavelet transform analysis gives the frequency and time-scale information. The neural network system as a fault detector was trained to discriminate HIF from the normal status by a gradient descent method. The proposed method performed very well by proving the right state when it was applied staged fault data and normal load mimics HIF, such as arc-welder.

• Journal of Electrical Engineering and Technology
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• 제2권1호
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• pp.29-34
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• 2007

The input and output impedances in a low voltage distribution system is one of the most important matters for power line communication because from the viewpoint of communication, the attenuation characteristic of the high frequency signals is greatly caused by impedance mismatch during sending and receiving. The frequency range is from 1MHz to 30MHz. Therefore, this paper investigates the input and output impedances in order to understand the characteristic of high frequency signals in the low voltage distribution system between a pole transformer and an end user. For power line communication, the model of Korea's low voltage distribution system is proposed in a residential area and then the low voltage distribution system is set up in a laboratory. In the low voltage distribution system, S parameters are measured by using a network analyzer. Finally, input and output impedances are calculated using S parameters.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 A
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• pp.487-490
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• 2002

Wind farm paralleled with electric power network can supply the power into a power network not only the normal conditions, but also the fault conditions of distribution network. If the fault happened in the power line with wind farm, the fault current level measured in a relaying point might be lower than that of distribution network without wind turbine generator. Consequently, it is difficult to detect the fault happened in the distribution network connected with wind generator. This paper describes the influence of wind turbine generator on the protective relaying system for detecting the fault occurred in a power line network. Simulation results shows that the fault current depends on the fault impedance, location, and the capacity of wind farm and distribution network load.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 B
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• pp.856-858
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• 1999

The analysis of distribution line faults is essential to the proper protection of power system. A high impedance fault(HIF) dose not make enough current to cause conventional protective device. It is well known that undesirable operating conditions and certain types of faults on electric distribution feeders cannot be detected by using conventional Protection system. This paper describes an algorithm using neural network for pattern recognition and detection of high impedance faults. Wavelet transform analysis gives the time-scale information. Time-scale representation of high impedance faults can detect easily and localize correctly the fault waveform.