• Title/Summary/Keyword: Power Distribution Network Impedance

Search Result 38, Processing Time 0.027 seconds

Criteria and Limitations for Power Rails Merging in a Power Distribution Network Design

  • Chew, Li Wern
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.20 no.4
    • /
    • pp.41-45
    • /
    • 2013
  • Modern electronic devices such as tablets and smartphones are getting more powerful and efficient. The demand in feature sets, functionality and usability increase exponentially and this has posed a great challenge to the design of a power distribution network (PDN). Power rails merging is a popular option used today in a PDN design as numerous power rails are no longer feasible due to form factor limitation and cost constraint. In this paper, the criteria and limitations for power rails merging are discussed. Despite having all the advantages such as pin count reduction, decoupling capacitors sharing, lower impedance and cost saving, power rails merging can however, introduce coupling noise to the system. In view of this, a PDN design with power rails merging that fulfills design recommendations and specifications such as noise target, power well placement, voltage supply values as well as power supply quadrant assignment is extremely important.

Estimation Method for Power Distribution Network of Impedance Characteristic on Printed Circuit Board (PCB상의 전력 배분망 설계를 위한 임피던스 계산법)

  • Cho Tae-ho;Park Joong-Ho;Baek Jong-Humn;Kim Seok-Yoon
    • The Transactions of the Korean Institute of Electrical Engineers D
    • /
    • v.52 no.4
    • /
    • pp.246-251
    • /
    • 2003
  • This paper proposes a new methodology for the estimation of impedance characteristics, which is one of the important issue in the power distribution network design of printed circuit boards. The modeling process of the proposed method divides the power distribution network into uniform segment, and each segment is modeled by distributed RLC transmission lines. Then, for the efficient computation of impedance characteristics in frequency domain. the proposed method uses a model-order reduction method.

Influence of the Interconnected Wind farm on Protection for Distribution Networks (풍력발전단지의 계통연계 운전이 배전선 보호계전에 미치는 영향)

  • 장성일;김광호
    • The Transactions of the Korean Institute of Electrical Engineers A
    • /
    • v.52 no.3
    • /
    • pp.151-157
    • /
    • 2003
  • Wind farm interconnected with grid can supply the power into a power network not only the normal conditions, but also the fault conditions of distribution network. If the fault happened in the distribution power line with wind fm, the fault current level measured in a relaying point might be lower than that of distribution network without wind turbine generator due to the contribution of wind farm. Consequently, it may be difficult to detect the fault happened in the distribution network connected with wind generator This paper describes the effect of the interconnected wind turbine generators on protective relaying of distribution power lines and detection of the fault occurred in a power line network. Simulation results shows that the current level of fault happened in the power line with wind farm depends on the fault impedance, the fault location. the output of wind farm. and the load condition of distribution network.

DRAM Package Substrate Using Via Cutting Structure (비아 절단 구조를 사용한 DRAM 패키지 기판)

  • Kim, Moon-Jung
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.48 no.7
    • /
    • pp.76-81
    • /
    • 2011
  • A new via cutting structure in 2-layer DRAM package substrate has been fabricated to lower its power distribution network(PDN) impedance. In new structure, part of the via is cut off vertically and its remaining part is designed to connect directly with the bonding pad on the package substrate. These via structure and substrate design not only provide high routing density but also improve the PDN impedance by shortening effectively the path from bonding pad to VSSQ plane. An additional process is not necessary to fabricate the via cutting structure because its structure is completed at the same time during a process of window area formation. Also, burr occurrence is minimized by filling the via-hole inside with a solder resist. 3-dimensional electromagnetic field simulation and S-parameter measurement are carried out in order to validate the effects of via cutting structure and VDDQ/VSSQ placement on the PDN impedance. New DRAM package substrate has a superior PDN impedance with a wide frequency range. This result shows that via cutting structure and power/ground placement are effective in reducing the PDN impedance.

Analysis of Chip Performance by Core and I/O SSN Noise on DLL Board (DLL 보드 상에 코어 및 I/O 잡음에 의한 칩의 성능 분석)

  • Cho, Sung-Gon;Ha, Jong-Chan;Wee, Jae-Kyung
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.13 no.4
    • /
    • pp.9-15
    • /
    • 2006
  • This paper shows the impedance profile of PEEC(Partial Equivalent Electrical Circuit) PDN(Power Distribution Networks) including core and I/O circuit. Through the simulated results, we find that the core power noise having connection with I/O power is affected by I/O switching. Also, using designed $74{\times}5inch$ DLL(Delay Locked Loop) test board, we analyzed the effect of power noise on operation region of chip. Jitter of a DLL measure for frequency of $50{\sim}400MHz$ and compared with impedance obtained result of simulation. Jitter of a DLL are increased near about frequency of 100MHz. It is reason that the resonant peak of PDNs has an impedance of more the 1ohm on 100MHz. we present the impedance profile of a chip and board for the decoupling capacitor reduced the target impedance. Therefore, power supply network design should be considered not only decoupling capacitors but also core switching current and I/O switching current.

  • PDF

Detection of High Impedance Fault based on Time Delay Neural Network (시간지연 신경회로망을 이용한 고장지락사고 검출)

  • Choi, Jin-Won;Lee, Chong-Ho;Kim, Choon-Woo
    • Proceedings of the KIEE Conference
    • /
    • 1994.11a
    • /
    • pp.405-407
    • /
    • 1994
  • In order to provide reliable power service and to prevent a potentail hazard and damage, it is important to detect high impedance fault in power distribution line. This paper presents a neural network based approach for the detection of high impedance faults. A time delay neural network has been selected and trained for the fault currents obtained from field experiments. Detection experiments have been performed with the data from four different high impedance surfaces. Experimental results indicated the feasibility of using TDNN for the detection of high impedance faults.

  • PDF

A Study on High Impedance Fault Detection using Wavelet Transform and Neural -Network (웨이브렛 변환과 신경망 학습을 이용한 고저항 지락사고 검출에 관한 연구)

  • Hong, Dae-Seung;Ryu, Chang-Wan;Yim, Wha-Yeong
    • The Transactions of the Korean Institute of Electrical Engineers A
    • /
    • v.50 no.3
    • /
    • pp.105-111
    • /
    • 2001
  • The research presented in this paper focuses on a method for the detection of High Impedance Fault(HIF). The method will use the wavelet transform and neural network system. HIF on the multi-grounded three-phase four-wires primary distribution power system cannot be detected effectively by existing over current sensing devices. These paper describes the application of discrete wavelet transform to the various HIF data. These data were measured in actual 22-9kV distribution system. Wavelet transform analysis gives the frequency and time-scale information. The neural network system as a fault detector was trained to discriminate HIF from the normal status by a gradient descent method. The proposed method performed very well by proving the right state when it was applied staged fault data and normal load mimics HIF, such as arc-welder.

  • PDF

Characteristic Impedances in Low-Voltage Distribution Systems for Power Line Communication

  • Kim, Young-Sung;Kim, Jae-Chul
    • Journal of Electrical Engineering and Technology
    • /
    • v.2 no.1
    • /
    • pp.29-34
    • /
    • 2007
  • The input and output impedances in a low voltage distribution system is one of the most important matters for power line communication because from the viewpoint of communication, the attenuation characteristic of the high frequency signals is greatly caused by impedance mismatch during sending and receiving. The frequency range is from 1MHz to 30MHz. Therefore, this paper investigates the input and output impedances in order to understand the characteristic of high frequency signals in the low voltage distribution system between a pole transformer and an end user. For power line communication, the model of Korea's low voltage distribution system is proposed in a residential area and then the low voltage distribution system is set up in a laboratory. In the low voltage distribution system, S parameters are measured by using a network analyzer. Finally, input and output impedances are calculated using S parameters.

The Study on Correction of Protective Relaying Set Value for the Power Electric Network Paralleled with Wind Farm (풍력전단지의 계통 연계 운전에 따른 보호 계전기 설정치 정정에 관한 고찰)

  • Jang, Sung-Il;Choi, Don-Man;Choi, Jeong-Hwan;Kim, Kwang-Ho;Oh, Jong-Youl;Kim, Joo-Yearl
    • Proceedings of the KIEE Conference
    • /
    • 2002.07a
    • /
    • pp.487-490
    • /
    • 2002
  • Wind farm paralleled with electric power network can supply the power into a power network not only the normal conditions, but also the fault conditions of distribution network. If the fault happened in the power line with wind farm, the fault current level measured in a relaying point might be lower than that of distribution network without wind turbine generator. Consequently, it is difficult to detect the fault happened in the distribution network connected with wind generator. This paper describes the influence of wind turbine generator on the protective relaying system for detecting the fault occurred in a power line network. Simulation results shows that the fault current depends on the fault impedance, location, and the capacity of wind farm and distribution network load.

  • PDF

A Study on High Impedance Fault Detection using Wavelet Transform and Neural-Network (웨이브릿 변환과 신경망 학습을 이용한 고저항 지락사고 검출에 관한 연구)

  • Hong, Dae-Seung;Ryu, Chang-Wan;Ko, Jae-Ho;Yim, Wha-Yeong
    • Proceedings of the KIEE Conference
    • /
    • 1999.07b
    • /
    • pp.856-858
    • /
    • 1999
  • The analysis of distribution line faults is essential to the proper protection of power system. A high impedance fault(HIF) dose not make enough current to cause conventional protective device. It is well known that undesirable operating conditions and certain types of faults on electric distribution feeders cannot be detected by using conventional Protection system. This paper describes an algorithm using neural network for pattern recognition and detection of high impedance faults. Wavelet transform analysis gives the time-scale information. Time-scale representation of high impedance faults can detect easily and localize correctly the fault waveform.

  • PDF