• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.189-197
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• 2014

This work proposes a 12b 100 MS/s $0.11{\mu}m$ CMOS three-step hybrid pipeline ADC for high-speed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dual-channel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a $0.11{\mu}m$ CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of $1.34mm^2$ and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.

• Journal of Radiation Protection and Research
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• v.41 no.2
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• pp.81-86
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• 2016

Background: For positron emission tomography (PET) application, cadmium zinc telluride (CZT) has been investigated by several institutes to replace detectors from a conventional system using photomultipliers or Silicon-photomultipliers (SiPMs). The spatial and energy resolution in using CZT can be superior to current scintillator-based state-of-the-art PET detectors. CZT has been under development for several years at the Korea Atomic Energy Research Institute (KAERI) to provide a high performance gamma ray detection, which needs a single crystallinity, a good uniformity, a high stopping power, and a wide band gap. Materials and Methods: Before applying our own grown CZT detectors in the prototype PET system, we investigated preliminary research with a developed discrete type data acquisition (DAQ) system for coincident events at 128 anode pixels and two common cathodes of two CZT detectors from Redlen. Each detector has a $19.4{\times}19.4{\times}6mm^3$ volume size with a 2.2 mm anode pixel pitch. Discrete amplifiers consist of a preamplifier with a gain of $8mV{\cdot}fC^{-1}$ and noise of 55 equivalent noise charge (ENC), a $CR-RC^4$ shaping amplifier with a $5{\mu}s$ peak time, and an analog-to-digital converter (ADC) driver. The DAQ system has 65 mega-sample per second flash ADC, a self and external trigger, and a USB 3.0 interface. Results and Discussion: Characteristics such as the current-to-voltage curve, energy resolution, and electron mobility life-time products for CZT detectors are investigated. In addition, preliminary results of gamma ray imaging using 511 keV of a $^{22}Na$ gamma ray source were obtained. Conclusion: In this study, the DAQ system with a CZT radiation sensor was successfully developed and a PET image was acquired by two sets of the developed DAQ system.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.35-41
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• 2000

This paper describes a merged-capacitor switching (MCS) technique to improve the signal Processing speed and resolution of CMOS analog-to-digital converters (ADCs). The proposed MCS technique improves a sampling rate by reducing the number of capacitors used in conventional pipelined ADCs. The ADC capacitor mismatch can be minimized without additional power consumption, die area, and the loss of sampling rate, when the size of each unit capacitor is increased as much as the number of capacitors reduced by the MCS technique. It is verified that the ADC resolution based on the proposed MCS technique is extended further by employing a conventional commutated feedback-capacitor switching (CFCS) technique.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.4
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• pp.393-400
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• 2014

In this paper, we have designed the transmitter for earth station terminal operating with military geostationary satellite on Ka-band that is complied with MIL-STD-188-164A. The designed antenna of this terminal is dual-offset gregorian reflector which is consist of corrugated horn and iris polarizer, othermode transducer. This antenna meets radiation pattern and transmit EIRP spectral density requirements in this standard. The designed RF systems of this terminal are consist of Block Up Converter(BUC) converting frequency band from IF to Ka band and SSPA having low-power consumption and compact light-weight using the pHEMT MMIC compound devices. This RF systems applied with VSWR, spurious/harmonic suppression, output flatness and phase noise requirement in this standard.

• Proceedings of the KIEE Conference
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• 2001.05a
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• pp.190-193
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• 2001

In order to verify the efficiency or availability and stability of photovoltaic(PV) generation systems, huge system apparatuses are needed, in general, in which an actual size of solar panel, a type of converter system and some amount of load facilities should be installed in a particular location. It is also hardly possible to compare a Maximum Power Point Tracking (MPPT) control scheme with others under the same weather and load conditions in an actual PV generation system. The only and a possible way to bring above-mentioned problem to be solved is to realize a transient simulation scheme for PV generation systems using real weather conditions such as insolation and surface temperature of solar cell. The authors, in this paper, introduces a novel simulation method, which is based on a real-time digital simulator (RTDS), for PV generation systems under the real weather conditions. Firstly, VI characteristic equation of a solar cell is developed as an empirical formula and reconstructed in the RTDS system, then the real data of weather conditions are interfaced to the analogue inputs of the RTDS. The outcomes of the simulation demonstrate the effectiveness of the proposed simulation scheme in this paper. The results shows that the cost effective verifying for the efficiency or availability and stability of PV generation systems and the comparison research of various control schemes like MPPT under the same real weather conditions are possible.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.5
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• pp.413-417
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• 2010

Line to ground faults by deterioration of insulators has frequently occurred in power system, and the main cause is surface contamination of the insulators. The contamination of insulator is analyzed by monitoring the surface leakage current flowing them. The suspension insulator is monitored by installation of a zero-phase current sensor(ZCT), but the line-post insulator is impossible to apply the same method because of its large diameter structure. This paper proposed a detection method of surface leakage current for a line-post insulator, and it can easily be applied to new and/or built insulators. The leakage current is indirectly calculated from the potential difference between the metal electrode attached on the surface of insulator and the ground connector. To evaluate the performance of the proposed method, the leakage current is compared as a function of contamination condition controlled by the density of NaCl solution. The leakage current is proportioned to the density of NaCl solution, and the voltage detected by the electrode showed the same trend. From the experimental results, we designed and fabricated a monitoring device which is composed of a detection electrode, signal converter, microprocessor, and ZigBee, and its measurement range is $10{\mu}A{\sim}5mA$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.1-8
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• 2009

We designed an ADC that operated upto 500Msamples/sec based on proposed R-string folding block as well as second folding block. The upper four bits are processed in parallel by the R-string folding block while the lower four bits are processed in pipeline structured second folding block to supply digital output. To verify the circuit performance, we conducted HSPICE simulation and the average power consumption was only 1.34mW even when the circuit was running at its maximum sampling frequency. We further measured noise immunity by applying linear ramp signal to the input. The DNL was between -0.56*LSB and 0.49*LSB and the INL was between -0.93*LSB and 0.72*LSB. We used 0.35 microns MOSIS device parameters for this work.

• Proceedings of the Korean Society of Medical Physics Conference
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• 2002.09a
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• pp.468-470
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• 2002

We have designed X-ray detection system and multi-channel data acquisition system for Spiral CT application. X-ray detection system consists of scintillator and photodiode. Scintillator converts X-ray into visible light. Photodiode converts visible light into electrical signal. The multi-channel data acquisition system consists of analog, digital, master and backplane board. Analog board detects electrical signal and amplifies signal by 140dB. Digital board consists of MUX(Multiplex) which routes multi-channel analog signal to preamplifier, and ADC(Analog to Digital Converter) which converts analog signal into digital signal. Master board supplies the synchronized clock and transmits the digital data to image reconstructor. Backplane provides electrical power, analog output and clock signal. The system converts the projected X-ray signal over the detector array with large gain, samples the data in each channel sequentially, and the sampled data are transmitted to host computer in a given time frame. To meet the timing limitation, this system is very flexible since it is implemented by FPGA(Field Programmable Gate Array). This system must have a high-speed operation with low noise and high SNR(signal to noise ratio), wide dynamic range to get a high resolution image.

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.128-133
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• 2006

This paper describes a high speed interface circuit using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that converts redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, the proposed 1:4 DEMUX (demultiplexer, serial-parallel converter), was designed using a 0.35um standard CMOS technology. Proposed DEMUX is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW. The operating speed of this circuit is limited by the maximum frequency which the 0.35um process has. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 10Gb/s in submicron process of high operating frequency.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.162-170
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• 2015

In the bandpass sampling (BPS), the sampling frequency is lower than the frequency of the signal to be sampled. In this method, the baseband spectrum can be directly obtained by the sampling operation. This makes the frequency down converter unnecessary as well as the receiver's circuit simpler. In the second-order BPS system, two sampling devices are used. When aliasing occurs due to the sampling operation, the aliased component can be cancelled by combining the two sampled signals. In this paper, it is presented a design method of the second-order BPS system when multiple interferences are simultaneously aliased to the signal component. The optimum phase of the interpolant filter is searched for maximizing the signal-to-interference ratio, and a practical formula for the suboptimal phase is derived in terms of the power spectrum profile of the BPS input. A computer simulation has been performed for the proposed second-order BPS system, and it has been shown that the signal-to-interference ratio can be increased by considering multiple aliasing.