• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1868-1876
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• 2010

In this paper, we design a 256-bit EEPROM IP using only logic process-based devices. We propose EEPROM core circuits, a control gate (CG) and a tunnel gate (TG) driving circuit, to limit the voltages between the devices within 5.5V; and we propose DC-DC converters : VPP (=+4.75V), VNN (-4.75V), and VNNL (=VNN/3) generation circuit. In addition, we propose switching powers, CG_HV, CG_LV, TG_HV, TG_LV, VNNL_CG, VNNL_TG switching circuit, to be supplied for the CG and TG driving circuit. Simulation results under the typical simulation condition show that the power consumptions in the read, erase, and program mode are $12.86{\mu}W$, $22.52{\mu}W$, and $22.58{\mu}W$ respectively. Furthermore, the manufactured test chip operated normally and generated its target voltages of VPP, VNN, and VNNL as 4.69V, -4.74V, and -1.89V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• Journal of Ocean Engineering and Technology
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• v.30 no.2
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• pp.84-90
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• 2016

In this study, a six degree-of-freedom motion analysis of a wind-wave hybrid platform equipped with numerous wave energy converters (WECs) was carried out. To examine the effect of the WECs on the platform, an analysis of one-way coupling was carried out, which only considered the power take-off (PTO) damping of the static WECs on the platform. The equation of motion of a floating platform with mooring lines in the time domain was established, and the responses of the one-way coupled platform were then compared with the case of a platform without any coupling effects from the WECs. The hydrodynamic coefficients and wave exciting forces were obtained from the 3D diffraction/radiation pre-processor code WAMIT based on the boundary element method. Then, an analysis of the dynamic responses of the floating platform with or without the WEC effect in the time domain was carried out. All of the dynamics of a floating platform with multiple wind turbines were obtained by coupling FAST and CHARM3D in the time domain, which was further extended to include additional coupled dynamics for multiple turbines. The analysis showed that the PTO damping effect on platform motions was negligible, but coupled effects between multiple WECs and the platform may differentiate the heave, roll, and pitch platform motions from the one without any effects induced by WECs.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5403-5408
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• 2012

In this paper, we introduce the multiple frequency bio-electrical impedance analysis method for body composition analysis. And then we implement the multiple frequency bio-electrical impedance analysis system. Overall system consists of: multiple frequency alternating current signal generator contained alternating current signal, phase signal detector, voltage signal detector, micro controller, in-out device(key-pad LCD), conductivity electrodes, system power. We explain the architecture of the system and required theory to implement the system. In order to investigate the clinical significance of the body composition data, compare to the data measured by the expert body composition analyzer which provide high reproduction and precision. Finally, experimental results which are the correlation between the measured data show the very high reproduction performance of the body composition analysis in the proposed system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.411-424
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• 2017

An all-digital delay-locked loop (DLL) for a mobile memory interface, which runs at 0.11-2.5 GHz with a phase-shift capability of $180^{\circ}$, has two internal DLLs: a global DLL which uses a time-to-digital converter to assist fast locking, and shuts down after locking to save power; and a local DLL which uses a phase detector with an adaptive phase sampling window (WPD) to reduce jitter accumulation. The WPD in the local DLL adjusts the width of its sampling window adaptively to control the loop bandwidth, thus reducing jitter induced by UP/DN dithering, input clock jitter, and supply/ground noise. Implemented in a 65 nm CMOS process, the DLL operates over 0.11-2.5 GHz. It locks within 6 clock cycles at 0.11 GHz, and within 17 clock cycles at 2.5 GHz. At 2.5 GHz, the integrated jitter is $954fs_{rms}$, and the long-term jitter is $2.33ps_{rms}/23.10ps_{pp}$. The ratio of the RMS jitter at the output to that at the input is about 1.17 at 2.5 GHz, when the sampling window of the WPD is being adjusted adaptively. The DLL consumes 1.77 mW/GHz and occupies $0.075mm^2$.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.79-85
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• 1999

In this paper, the resistive mixer for 5.86Hz wireless LAN, main part receiving system, was designed and implemented. The noise characteristics and the linearity in the base band was superior. For the use of local oscillator of mixer, dielectric resonator of stable output and temperature characteristics was designed. For the electrical tuning by the capacitance variation of varactor diode, the microstrip line and magnetic coupling characteristics of the dielectric resonance was used. It was obtained that gain of the proposed resistive mixer containing the RF cable loss, is -13.8dB, the conversion loss of frequency converter is -12 dB, and the output power of local oscillator is 1.67 dBm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.658-665
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• 2014

The neural stimulators have been employed to the visual prostheses system based on the functional electrical stimulation (FES). Due to the size limitation of the implantable device, the smaller area of the unit current driver pixel is highly desired for higher resolution current stimulation system. This paper presents a 16-channel compact current-mode neural stimulator IC with digital to analog converter (DAC) sharing scheme for artificial retinal prostheses. The individual pixel circuits in the stimulator IC share a single 6 bit DAC using the sample-and-hold scheme. The DAC sharing scheme enables the simultaneous stimulation on multiple active pixels with a single DAC while maintaining small size and low power. The layout size of the stimulator circuit with the DAC sharing scheme is reduced to be 51.98 %, compared to the conventional scheme. The stimulator IC is designed using standard $0.18{\mu}m$ 1P6M process. The chip size except the I/O cells is $437{\mu}m{\times}501{\mu}m$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.7
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• pp.655-661
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• 2006

Dielectric and piezoelectric properties of PMN-PZT ceramics with a high mechanical quality factor$(Q_m)$ and a low temperature sintering temperature were investigated as a function of PZN substitution in order to develop multilayer piezoelectric transformer for AC-DC converter. Multilayer piezoelectric transformers were subsequently manufactured using the PMN-PZN-PZT ceramic offering the optimal behavior and then the electrical performance were invetigated. At the sintering temperature of $940^{\circ}C$, density, electromechanical coupling factor$(k_p)$, mechanical qualify factor$(Q_m)$ and dielectric constant$(\varepsilon_r)$ of 8 mol% PZN substituted specimen were $7.73g/cm^3$, 0.524, 1573 and 1455, respectively. The PZN substitution caused a increase in the dielectric constant and the electromechnical coupling factor. The voltage step-up ratio of multilayer piezoelectric transformer showed the maximum value at near the resonant frequency of 76.55 kHz and increased according to the increase of load resistance. The multilayer piezoelectric transformer with the output impedance coincided with the load resistance showed the temperature increase of less than $20^{\circ}C$ at the output power of 10 W. Based on the results, the manufactured multilayer transformer using the low temperature sintered PMN-PZN-PZT ceramics can be stably driven for both step-up and down transformers.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.2
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• pp.81-89
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• 1999

Among various wavelength conversion technologies, that using the cross-gain modulation in laser diode makes it possible to deal with the high speed signal quite simply and efficiently. In this paper, presented was the applicability of an improved time-domain large-signal dynamic model as a CAD tool to analyzed the characteristics of SSGDBR(Superstructure Grating Distributed Bragg Reflector) laser diodes used for wavelength converters. Using this model, it was shown that this kind of wavelength converter can provide the widely tunable wavelength conversion of the high speed data above 10 Gbps. We also investigated the effect of input optical power and the bias current on the characteristics of the device such as extinction ration and eye diagram. The modeling results show very similar trend to the experimental reports.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.8
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• pp.784-790
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• 2009

A forward-looking automotive radar typically utilizes the frequency modulated continuous wave(FMCW) or pulsed-Doppler waveform for the Information acquisition of the target range and velocity. In order to obtain the high resolution target information, however, a narrow pulse width and wide bandwidth are inherently required, thus resulting in high peak power and high speed digital converter processing. In this paper, a stepped-frequency pulsed-Doppler(SFPD) waveform algorithm is proposed for high resolution forward looking automotive radar application. The performance of the proposed SFPD waveform technique is analyzed and compared with the conventional FMCW and PD method. Since this technique can be used for the high resolution target imaging with arbitrary range and Doppler resolution, it is expected to be useful In automotive radar target classification for the precision collision avoidance applications in the future.