• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1847-1855
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• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.2 s.302
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• pp.49-58
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• 2005

A new soft switching three-phase PWM rectifier with simple circuit configuration and high efficiency has been developed. The proposed circuit is a kind of the auxiliary resonant commutated Pole(ARCP)converter The conventional ARCP converter requires three-auxiliary reactors and six-auxiliary switches for the soft switching auxiliary circuit and for these switching elements, a gate drive circuit and a control circuit are required, resulting in high part as a disadvantage. In the main circuit proposed in this paper, the auxiliary soft switching circuit is composed of two-auxiliary reactors, two-auxiliary switches and several diodes. In addition, common use of the PWM control circuit for two-switches will make the control circuit of the auxiliary switches simple. By means of function of the soft switching auxiliary circuit, the main switching element performs zero voltage switching operation and the auxiliary switches perform the zero current switching. In this paper, the circuit configuration and the operational analysis of the proposed circuit are described at first and then, experimental results will be reported. By using a prototype with 5[kW] capacity, the conversion efficiency of maximum $98.8[\%]$ and the power factor of $99[\%]$ or higher were obtained.

• Annals of Clinical Neurophysiology
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• v.13 no.2
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• pp.80-86
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• 2011

Background: A dry-type electrode is an alternative to the conventional wet-type electrode, because it can be applied without any skin preparation, such as a conductive electrolyte. However, because a dry-type electrode without electrolyte has high electrode-to-skin impedance, an impedance-converting amplifier is typically used to minimize the distortion of the bioelectric signal. In this study, we developed an active dry electroencephalography (EEG) electrode using an impedance converter, and compared its performance with a conventional Ag/AgCl EEG electrode. Methods: We developed an active dry electrode with an impedance converter using a chopper-stabilized operational amplifier. Two electrodes, a conventional Ag/AgCl electrode and our active electrode, were used to acquire EEG signals simultaneously, and the performance was tested in terms of (1) the electrode impedance, (2) raw data quality, and (3) the robustness of any artifacts. Results: The contact impedance of the developed electrode was lower than that of the Ag/AgCl electrode ($0.3{\pm}0.1$ vs. $2.7{\pm}0.7\;k{\Omega}$, respectively). The EEG signal and power spectrum were similar for both electrodes. Additionally, our electrode had a lower 60-Hz component than the Ag/AgCl electrode (16.64 vs. 24.33 dB, respectively). The change in potential of the developed electrode with a physical stimulus was lower than for the Ag/AgCl electrode ($58.7{\pm}30.6$ vs. $81.0{\pm}19.1\;{\mu}V$, respectively), and the difference was close to statistical significance (P=0.07). Conclusions: Our electrode can be used to replace Ag/AgCl electrodes, when EEG recording is emergently required, such as in emergency rooms or in intensive care units.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.149-155
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• 2015

This paper proposes 5-MS/s 10-bit digital-to-analog converter(DAC) with the improved linearity. The proposed DAC consists of a 10-bit R-2R-based DAC, an output buffer using a differential voltage amplifier with rail-to-rail input range, and a band-gap reference circuit for the bias voltage. The linearity of the 10-bit R-2R DAC is improved as the resistor of 2R is implemented by including the turn-on resistance of an inverter for a switch. The output voltage range of the DAC is determined to be $2/3{\times}VDD$ from an rail-to-rail output voltage range of the R-2R DAC using a differential voltage amplifier in the output buffer. The proposed DAC is implemented using a 1-poly 8-metal 130nm CMOS process with 1.2-V supply. The measured dynamic performance of the implemented DAC are the ENOB of 9.4 bit, SNDR of 58 dB, and SFDR of 63 dBc. The measured DNL and INL are less than +/-0.35 LSB. The area and power consumption of DAC are $642.9{\times}366.6{\mu}m^2$ and 2.95 mW, respectively.

• Journal of IKEEE
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• v.23 no.1
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• pp.35-43
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• 2019

A capacitor self-calibration is proposed to improve the linearity of the capacitor digital-to-analog converter (CDAC) for an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with 10-bit resolution. The proposed capacitor self-calibration is performed so that the value of each capacitor of the upper 5 bits of the 10-bit CDAC is equal to the sum of the values of the lower capacitors. According to the behavioral simulation results, the proposed capacitor self-calibration improves the performances of differential nonlinearity (DNL) and integral nonlinearity (INL) from -0.810/+0.194 LSBs and -0.832/+0.832 LSBs to -0.235/+0.178 LSBs and -0.227/+0.227 LSBs, respectively, when the maximum capacitor mismatch of the CDAC is 4%. The proposed 10-bit 20-MS/s asynchronous SAR ADC is implemented using a 110-nm CMOS process with supply of 1.2 V. The area and power consumption of the proposed asynchronous SAR ADC are $0.205mm^2$ and 1.25 mW, respectively. The proposed asynchronous SAR ADC with the capacitor calibration has a effective number of bits (ENOBs) of 9.194 bits at a sampling rate of 20 MS/s about a $2.4-V_{PP}$ differential analog input with a frequency of 96.13 kHz.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.51-57
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• 2015

In this paper, in order to design the A / D converter with a high resolution of 14 bits or more for the biological signal processing, CMOS delta sigma modulator that is a 1.8V power supply voltage - were designed. we propose a new structure of The fourth order delta-sigma modulator that needs four op amps but we use only two op amps. By using a time -interleaving technique, we can re-construct the circuit and reuse the op amps. Also, we proposed a KT/C noise reduction circuit to reduce the thermal noise from a noisy resistor. We adjust the size of sampling capacitor between sampling time and integrating time, so we can reduce almost a half of KT/C noise. The measurement results of the chip is fabricated using a Magna 0.18um CMOS n-well1 poly 6 metal process. Power consumption is $828{\mu}W$ from a 1.8V supply voltage. The peak SNDR is measured as a 75.7dB and 81.3dB of DR at 1kHz input frequency and 256kHz sampling frequency. Measurement results show that KT/C noise reduction circuit enhance the 3dB of SNDR. FOM of the circuit is calculated to be 142dB and 41pJ / step.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.5 s.108
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• pp.476-482
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• 2006

In this paper, a multimode feed horn antenna is suggested for a high power microwave(HPM) antenna system. The proposed HPM feed horn antenna which is connected with a mode converter is located between source and reflector antenna. A multimode feed horn antenna which has reduced -25 dB beamwidth is designed and fabricated for miniaturization of reflector antenna because -25 dB beamwidth which is determined by considering spillover of feed horn antenna decides a size of reflector in case of HPM. As a result, feed system which uses the multimode feed horn antenna has high gain about 27 dBi and return loss is less than -22 dB at 10 GHz. The measured -25 dB beamwidths of the radiation pattern at vertical, horizontal-plane equal to $20.24^{\circ},\;28.92^{\circ}$ which is less than about $10^{\circ}$ beamwidth of conventional feed system. Thus the suggested feed hem antenna is suitable to feed horn for miniaturization of HPM antenna system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.843-852
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• 2009

In this paper, we present design, fabrication, and measured results for a frequency upconverter for a wireless communication system of UAV(Unmanned Aerial Vehicle). The specifications of such wireless communication system requires the special features of maximum range of communication as well as deployment in UAV and repairing. The frequency upconverter operating at $5.25{\sim}5.45\;GHz$ in C-band was designed and fabricated considering such special features. The AGC function was included because the required output power should be constant for optimal system operation. The fabricated upconverter showed a constant output power of $+2{\pm}0.5\;dBm$ for the $-15{\sim}-10\;dBm$ input. Spuriouses were below -60 dBc and the adjacent leakage power was below -40 dBc. In addition, LO sources in the upconverter was implemented using the frequency synthesizer with step 1 MHz. This is for the application to the situation where multiple UAVs employed and the possible change of the permitted frequency band. The synthesizer showed a phase noise of -100 dBc/Hz at the 100 kHz frequency offset.

• Journal of Navigation and Port Research
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• v.40 no.3
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• pp.159-164
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• 2016

The goal of this study is to implement a communication system that can monitor the status of the nacelle using the power cable itself, without the dedicated communication lines such as an UTP cable and optical fiber for the offshore wind turbine. An inductive coupling powerline communication system for a MW class offshore wind turbine was proposed and its communication performance was demonstrated. The inductive couplers was designed for operation at up to 500 A using a ferrite composite materials. Field test was carried out on the wind farms of Jeju island. Using the iperf communication test program, we have obtained more than 15 Mbps data transmission rate through the 100 m power cable that was installed between the nacelle and the bottom of the power converter. In the data transmission stability test for a week, there was no failure ever. The minimum transmission rate was 15 Mbps and the average data rate was about 20 Mbps. Next, we have installed an infrared camera inside the nacelle in order to measure the temperature distribution and variation of the nacelle. The real-time thermal image taken by the camera was successfully sent to the monitoring system without error.