• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.241-246
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 $M{\sim}725$ MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

• 전기학회논문지P
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• 제52권4호
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• pp.172-178
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• 2003

This paper examines the application of high voltage static var compensator(SVC) with cascade multilevel inverter which employs H-bridge inverter(HBI). This method has the primary advantage that the number of voltage levels can be increased for a given number of semiconductor devices when compared to the conventional control methods. The SVC system is modeled using the d-q transform which calculates the instantaneous reactive power. This model is used to design a controller and analyze the SVC system. From the mathematical model of the system, the design procedures of the circuit parameters L and C are presented in this thesis. To meet the specific total harmonic distortion(THD) and ripple factor of the capacitor voltage, the circuit parameters L and C are designed. Simulated and experimental results are also presented and discussed to validate the proposed schemes.

• Journal of Electrical Engineering and Technology
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• 제12권5호
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• pp.1805-1811
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• 2017

Recently, DC systems are considered as efficient electric power systems for renewable energy based clean power generators. This discloses several critical issues that are required to be considered before the installation of the DC systems. First of all, voltage/current switching stress, which is aggravated by large fault current, might damage DC circuit breakers. This problem can be simply solved by applying a superconducting fault current limiter (SFCL) as proposed in this study. It allows a simple use of insulated-gate bipolar transistors (IGBTs) as a DC circuit breaker. To evaluate the proposed resistive type SFCL application to the DC circuit breaker, a DC distribution system is composed of the practical line impedances from the real distribution system in Do-gok area, Korea. Also, to reflect the distributed generation (DG) effects, several DC-to-DC converters are applied. The locations and sizes of the DGs are optimally selected according to the results of previous studies on DG optimization. The performance of the resistive type SFCL applied DC circuit breaker is verified by a time-domain simulation based case study using the power systems computer aided design/electromagnetic transients including DC (PSCAD/ EMTDC(R)).

• 센서학회지
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• 제26권5호
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• pp.331-337
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• 2017

A readout circuit for a tactile sensor pad based on force sensing resistors was proposed, which was composed of an analog signal conditioning circuit and a digital circuit with a microcontroller. The conventional signal conditioning circuit has a dc offset voltage in the output signal, which results from the reference voltage applied to the FSR devices. The offset voltage reduces the dynamic range of the circuit and makes it difficult to operate the circuit under a low voltage power supply. In the proposed signal conditioning circuit, the dc offset voltage was removed completely. The microcontroller with A/D converter and D/A converter was used to enlarge the measurement range of pressure. For this, the microcontroller adjusts the FSR reference voltage according to the resistance magnitude of FSR under pressure. The operation of the proposed readout circuit which was connected to a tactile sensor pad with $5{\times}10$ FSR array was verified experimentally. The experimental results show the proposed readout circuit has the wider measurement range of pressure than the conventional circuit. The proposed circuit is suitable for low voltage and low power applications.

• 전자공학회논문지D
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• 제36D2호
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• pp.71-80
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• 1999

본 논문에서는 2${\mu}m$ 고전압 CMOS 공정을 사용한 보호 회로를 포함한 전력 ,MOSFET 구동기를 설계하였다. 제어 회로의 안정한 동작을 위하여 전원 관리 회로를 설계하였으며 전원 관리 회로의 전압 레귤레이터의 보호를 위하여 전압 검출 방식의 단락 보호 회로를 제안하였다. 전압 검출 방식(Voltage-Detection Short Circuit Protection; VDSCP)은 직렬 저항에 의한 전압 강하가 없고, 출력단 단락 상태에서 전압원의 전류를 출력단에 흐르지 못하도록 하는 특성이 있다. 전력 MOSFET를 보호하기 위하여 부하 단락 보호회로, 게이트 전압 제한 회로, 과전압 보호 회로를 설계하였으며, 50V의 항목 전압을 닺는 공정을 이용하여 전력 MOSFET 구동기를 위한 2${\mu}m$ 고전압 CMOS 공정을 개발하였다. 전력 MOSFET이 소비하는 전력 이외에 구동기가 소비하는 전력은 전력 MOSFET 구동 상태에 따라 20 ~ 100mW의 범위에 있는 것으로 확인하였다. 주문형으로 제작된 전력 MOSFET 구동기의 active area의 크기는 $3.5 {\times}2..8mm^2$이다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 B
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• pp.958-960
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• 2002

High Temperature Superconducting (HTS) devices make it possible to operate with no electrical loss by resistance. If, however, the applied current is over its critical current, the phase of HTS devices is changed to normal state, so called, quench. In this case, since resistance of HTS is increased abruptly, it can not be avoidable to damage the whole apparatus. In this study, quench detector to protect HTS devices was proposed. We designed the quench detecting circuit and tested the performance of the circuit. The detecting circuit was consisted of Op-Amp and low pass filter etc, to detect very low voltage around $1{\mu}V$. The circuit detected effectively the low voltage when over current is applied to HTS tapes. At the next step, we are going to apply and test the circuit to protect the prototype HTS cable.

• 전력전자학회논문지
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• 제21권4호
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• pp.335-342
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• 2016

This paper proposes an energy storage-assisted, series-connected module-integrated power conversion system that integrates a photovoltaic power conditioner and a charge balancing circuit. In conventional methods, a photovoltaic power conditioner and a cell-balancing circuit are needed for photovoltaic systems with energy storage devices, but they cause a complex configuration and high cost. Moreover, an imbalanced output voltage of the module-integrated converter for PV panels can be a result of partial shading. Partial shading can lead to the fault condition of the boost converter in shaded modules and high voltage stresses on the devices in other modules. To overcome these problems, a bidirectional buck-boost converter with an integrated magnetic device operating for a charge-balancing circuit is proposed. The proposed circuit has multiple secondary rectifiers with inductors sharing a single magnetic core, which works as an inductor for the main bidirectional charger/discharger of the energy storage. The secondary rectifiers operate as a cell-balancing circuit for both energy storage and the series-connected multiple outputs of the module-integrated converter. The operating principle of the cell-balancing power conversion circuit and the power stage design are presented and validated by PSIM simulation for analysis. A hardware prototype with equivalent photovoltaic modules is implemented for verification. The results verify that the modularized photovoltaic power conversion system in the output series with an energy storage successfully works with the proposed low-cost bidirectional buck-boost converter comprising a single magnetic device.

• 전자공학회논문지SC
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• 제38권3호
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• pp.40-46
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• 2001

본 논문에서는 10개의 트랜지스터를 이용한 새로운 저전력 전가산기의 회로를 제안한다. 회로는 six-transistor CMOS XOR 회로를 기본으로 하여 XOR 출력뿐만 아니라 XNOR 출력을 생성하며, 전가산기를 구성하는 트랜지스터의 수를 줄임과 동시에 단락회로를 없앰으로써 저전력 설계에 유리하게 하였다. 실측 회로의 크기 평가를 위해서 0.65 ${\mu}m$ ASIC 공정으로 의해 레이아웃을 하고 HSPICE를 이용해서 시뮬레이션을 하였다. 제안한 가신기의 셀을 이용하여 2bit， 8bit 리플 캐리 가산기를 구성하여 소비 전력, 지연 시간, 상승시간, 하강시간에 대한 시뮬레이션 결과로 제안한 회로를 검증하였다. 25MHz부터 50MHz까지의 클럭을 사용하였다. 8bit 리플 캐리 전가산기로 구현하였을 때의 소모되는 전력을 살펴보면 기존의 transmission function full adder (TFA) 설계보다는 약 70% 정도, 그리고 14개의 transistor (TR14)[4]를 쓰는 설계보다는 약 60% 우수한 특성을 보이고 있다. 또한 신호의 지연시간은 기존의 회로, TFA, TR14 보다 1/2배 정도 짧고, 선호의 상승시간과 하강 시간의 경우는 기존 회로의 2${\sim}$3배 정도 빠르게 나타났다.

• 한국위성정보통신학회논문지
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• 제10권1호
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• pp.77-82
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• 2015

본 논문에서는 LED 형광등에 활용이 가능한 컨버터 관한 연구를 수행하였다. 기존 고효율에너지 기자재로 지정된 형광램프용 고조도 반사갓이 LED 형광램프의 Heat-sink 구조상 활용할 수 없는 구조이기 때문에 LED 형광램프 컨버터의 에너지 효율이 뛰어난 회로 설계 및 보호회로 설계가 필요하다. 따라서 본 논문에서는 직관형 LED램프 컨버터에 회로구동방식을 적용한 LED 형광등 연구를 수행하였다. 또한, LED를 광원으로 한 'LED 램프'와 일반 상용 전원에 접속해 직류 전원을 공급할 수 있는 컨버터에 대하여 설계 및 제작을 하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.133-136
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• 2001

A new package design method to reduce resonance effect due to an IC package is represented. Frequency-variant circuit model of the power/ground plane was developed to accurately reflect the resonance. The circuit model is benchmarked with a full wave simulation, thereby verifying its accuracy. Then it was shown that the proposed technique can efficiently reduce the resonance due to the IC package.