• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.11-19
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• 1999

Fractal image compression algorithm has been studied mostly not in the view of hardware but software. However, a general processor by software can't decode fractal compressed images in real-time. Therefore, it is necessary that we develop a fast dedicated hardware. However, design examples of dedicated hardware are very rare. In this paper, we designed a quadtree fractal-based compressed image decoder which can decode $256{\times}256$ gray-scale images in real-time and used two power-down methods. The first is a hardware-optimized simple post-processing, whose role is to remove block effect appeared after reconstruction, and which is easier to be implemented in hardware than non-2' exponents weighted average method used in conventional software implementation, lessens costs, and accelerates post-processing speed by about 69%. Therefore, we can expect that the method dissipates low power and low energy. The second is to design a power dissipation in the multiplier can be reduced by about 28% with respect to a general array multiplier which is known efficient for low power design in the size of 8 bits or smaller. Using the above two power-down methods, we designed decoder's core block in 3.3V, 1 poly 3 metal, $0.6{\mu}m$ CMOS technology.

• Journal of IKEEE
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• v.24 no.1
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• pp.161-169
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• 2020

In order to reduce the manufacturing cost of MCU chips used in applications such as wireless chargers and USB-C, compared to DP-EEPROM (Double Poly EEPROM), which requires 3 to 5 additional process masks, it is even more necessary MTP(Multi-Time Programmable), which is less than one additional mask and have smaller unit cell size. In addition, in order to improve endurance characteristics and data retention characteristics of the MTP memory cell due to E/P(Erase / Program) cycling, the distribution of the V_TP(Program Threshold Voltage) and the V_TE(Erase Threshold Voltage) needs to be narrow. In this paper, we proposed a current-type BL S/A(Bit-Line Sense Amplifier) circuit, WM(Write Mask) circuit, BLD(BL Driver) circuit and a algorithm, which can reduce the distribution of program and V_T and erase V_T, through compare the target current by performing the erase and program pulse of the short pulse several times, and if the current specification is satisfied, the program or erase operation is no longer performed. It was confirmed that the 256Kb MTP memory fabricated in the Magnachip semiconductor 0.13㎛ process operates well on the wafer in accordance with the operation mode.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.5
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• pp.538-542
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• 2018

Echo generated in digital hearing aid vent give rise to user's discomfort. For cancelling feedback echo in vent, it is required to estimate vent impulse response exactly. The vent impulse response has time varying and sparse characteristics. The IPNLMS has been known a useful adaptive algorithm to estimate vent impulse response with these characteristics. In this paper, subband sparse adaptive filter which applying IPNLMS to subband hearing aid structure is proposed to cancel echo of vent by estimating sparse vent impulse response. In the propose method, the decomposition of input signal to subband can pre-whiten each subband signal, so adaptive filter convergence speed can be improved. And the poly phase component decomposition of adaptive filter increases sparsity of each components, and the better echo cancellation can be possible without additional computation. To derive coefficients update equation of the adaptive filter, by defining the cost function based weight NLMS is defined, and the coefficient update equation of each subband is derived. For verifying performances of the adaptive filter, convergence speed, and steady state error by white signal input, and echo cancelling results by real speech input are evaluated by comparing conventional adaptive filters.