• 한국태양에너지학회:학술대회논문집
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• 한국태양에너지학회 2008년도 춘계학술발표대회 논문집
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• pp.252-256
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• 2008

Photovoltaic (PV) modules output changes noticeable with variations in temperature and irradiance. In general it is has been shown that a $1^{\circ}C$ increase in temperature results in a 0.5% drop in output. In this paper, seven PV module types are analyzed for variation in temperature and irradiance, and the resulting output characteristics examined. The 7 modules types utilized are as follows; 3 poly crystalline modules, 2 single crystalline modules, 1 back contact single crystalline module and 1 HIT module. 3 groups of experiments are then conducted on the modules; tests with varying irradiance values, tests with module temperature varying under $25^{\circ}C$ and tests with module temperature varying over $25^{\circ}C$. The experiments results show that as temperature rises the follow is observed; Pmax decreases by 0.6%, Voc decreases by about 0.4%, and Isc increasing by between 0.03%${\sim}$0.08%. In addition, an irradiance decrease of 100 w/m2 translates into a 10% drop in Pmax.

• 한국전기전자재료학회논문지
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• 제11권2호
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• pp.106-110
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• 1998

The $LiNbO_3$ thin films were prepared directly on Si(100) substrates by conventional RF magnetron spurttering system for nonvolatile memory applications. RTA(Rapid Thermal Annealing) treatment was performed for as-deposited films in an oxygen atmosphere at 600 $^{\circ}C$ for 60 s. The rapid thermal annealed films were changed to poly-crystalline ferroelectric nature from amorphous of as-deposition. The resistivity of the ferroelectric $LiNbO_3$ film was increased from a typical value of $1{\sim}2{\times}10^8{\Omega}{\cdot}cm$ before the annealing to about $1{\times}10^{13}{\Omega}{\cdot}cm$ at 500 kV/cm and reduced the interface state density of the $LiNbO_3/Si$ (100) interface to about $1{\times}10^{11}/cm^2{\cdot}eV$. Ferroelectric hysteresis measurements using a Sawyer-Tower circuit yielded remanent polarization ($P_r$) and coercive field ($E_c$) values of about 1.2 ${\mu}C/cm^2$ and 120 kV/cm, respectively.

• Journal of Industrial and Engineering Chemistry
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• 제68권
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• pp.173-179
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• 2018

Electrochemical characterization was conducted on poly(vinyl alcohol) (PVA)-ceramic composite (PVA-CC) separators for supercapacitor applications. The PVA-CC separators were fabricated by mixing various ceramic particles including aluminum oxide ($Al_2O_3$), silicon dioxide ($SiO_2$), and titanium dioxide ($TiO_2$) into a PVA aqueous solution. These ceramic particles help to create amorphous regions in the crystalline structure of the polymer matrix to increase the ionic conductivity of PVA. Supercapacitors were assembled using PVA-CC separators with symmetric activated carbon electrodes and electrochemical characterization showed enhanced specific capacitance, rate capability, cycle life, and ionic conductivity. Supercapacitors using the $PVA-TiO_2$ composite separator showed particularly good electrochemical performance with a 14.4% specific capacitance increase over supercapacitors using the bare PVA separator after 1000 cycles. With regards to safety, PVA becomes plasticized when immersed in 6 M KOH aqueous solution, thus there was no appreciable loss in tear resistance when the ceramic particles were added to PVA. Thus, the enhanced electrochemical properties can be attained without reduction in safety making the addition of ceramic nanoparticles to PVA separators a cost-effective strategy for increasing the ionic conductivity of separator materials for supercapacitor applications.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.406-406
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• 2016

To get high efficiency n-type crystalline silicon solar cells, passivation is one of the key factor. Tunnel oxide (SiO2) reduce surface recombination as a passivation layer and it does not constrict the majority carrier flow. In this work, the passivation quality enhanced by different chemical solution such as HNO3, H2SO4:H2O2 and DI-water to make thin tunnel oxide layer on n-type crystalline silicon wafer and changes of characteristics by subsequent annealing process and firing process after phosphorus doped amorphous silicon (a-Si:H) deposition. The tunneling of carrier through oxide layer is checked through I-V measurement when the voltage is from -1 V to 1 V and interface state density also be calculated about $1{\times}1012cm-2eV-1$ using MIS (Metal-Insulator-Semiconductor) structure . Tunnel oxide produced by 68 wt% HNO3 for 5 min on $100^{\circ}C$, H2SO4:H2O2 for 5 min on $100^{\circ}C$ and DI-water for 60 min on $95^{\circ}C$. The oxide layer is measured thickness about 1.4~2.2 nm by spectral ellipsometry (SE) and properties as passivation layer by QSSPC (Quasi-Steady-state Photo Conductance). Tunnel oxide layer is capped with phosphorus doped amorphous silicon on both sides and additional annealing process improve lifetime from $3.25{\mu}s$ to $397{\mu}s$ and implied Voc from 544 mV to 690 mV after P-doped a-Si deposition, respectively. It will be expected that amorphous silicon is changed to poly silicon phase. Furthermore, lifetime and implied Voc were recovered by forming gas annealing (FGA) after firing process from $192{\mu}s$ to $786{\mu}s$. It is shown that the tunnel oxide layer is thermally stable.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.2
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• pp.1034-1037
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• 2003

Microcrystalline silicon(c-Si:H) thin-film solar cells are prepared with intrinsic Si-layer by hot wire CVD. The operating parameters of solar cells are strongly affected by the filament temperature ($T_f$) during intrinsic layer. Jsc and efficiency abruptly decreases with elevated $T_f$ to $1400^{\circ}C$. This deterioration of solar cell parameters are resulted from increase of crystalline volume fraction and corresponding defect density at high $T_f$. The heater temperature ($T_h$) are also critical parameter that controls device operations. Solar cells prepared at low $T_h$ ($<200^{\circ}C$) shows a similar operating properties with devices prepared at high $T_f$, i.e. low Jsc, Voc and efficiency. The origins for this result, however, are different with that of inferior device performances at high $T_f$. In addition the phase transition of the silicon films occurs at different silane concentration (SC) by varying filament temperature, by which highest efficiency with SC varies with $T_f$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1997년도 추계학술대회 논문집
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• pp.21-24
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• 1997

Ferroeletric LiNbO$_3$ thin films hale been prepared directly on Si(100) substrates by conventional RF magnetron spurttering system for nonvolatile memory applications. As-deposited films were performed RTA(Rapid Thermal Annealing) treatment in an oxygen atmosphere at 600 $^{\circ}C$ for 60 s. The rapid thermal annealed films were changed to poly-crystalline ferroelectric nature from amorphous of as-deposition. The resistivity of the ferroelectric LiNbO$_3$ film was increased from a typical vague of 1~2$\times$10$^{8}$ $\Omega$.cm before the annealing to about 1$\times$10$^{13}$ $\Omega$.cm at 500 kV/cm and reduce the interface state density of the LiNbO$_3$/Si(100) interface to about 1$\times$10$^{11}$ cm$^2$ . eV. Ferroelectric hysteresis measurements using a Sawyer-Tower circuit yielded remanent polarization (Pr) and coercive field (Ec) values of about 1.2 $\mu$C/cm$^2$ and 120 kV/cm, respectively.

• Korean Chemical Engineering Research
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• 제58권3호
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• pp.369-380
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• 2020

대부분의 단결정 실리콘 잉곳은 초크랄스키(Czochralski(Cz)) 공정으로 제조된다. 그러나 단결정 실리콘 잉곳을 제품화 및 태양 전지 기판으로 가공하였을 때 산소 불순물이 있는 경우 낮은 효율성을 나타내는 경향이 있다. 단결정 Si-잉곳의 생산을 위해서는 용융 Si를 녹인 다음 단결정 Si의 시드(Seed)로 결정화하는 초크랄스키(Cz) 공정을 도입한다. 용융된 다결정 Si-덩어리를 단결정 Si-잉곳으로 결정성장 될 때, 열 전달은 Cz-공정의 구조에서 중요한 역할을 한다. 본 연구에서 고품질 단결정 실리콘 잉곳을 얻기 위해 Cz-공정의 최적화된 설계를 구성하였다. 결정 성장 시뮬레이션로부터 결정성장을 위한 Pulling rate 및 Rotation speed에 최적의 변수값을 형성하기 위해 사용되었으며, 변형된 Cz-공정에 대한 연구 및 해당 결과가 논의되며 결정 성장 시뮬레이션을 사용하여 Cz-공정의 Pulling rate, Rotation speed 및 Melt charge level의 최적화된 설계로 인한 결정성장시 단결정 실리콘으로 유입되는 산소 농도 최소화를 설계하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.279.1-279.1
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• 2016

박막 트랜지스터 (thin film transistor, TFT)는 고밀도, 대면적화로 높은 전자의 이동도가 요구되면서, 비정질 실리콘 (a-Si)에서 다결정 실리콘 (poly-Si) TFT 로 연구되었다. 이에 따라 비정질 실리콘에서 결정질 실리콘으로의 상변화에 대한 결정화 연구가 활발히 진행되었다. 또한, 박막 태양전지 분야에서도 유리기판 위에 비정질 층을 증착한 후에 열처리를 통해 상변화하는 고상 결정화 (solid-phase crystallization, SPC) 기술을 적용하여, CSG (thin-film crystalline silicon on glass) 태양전지를 보고하였다. 이러한 비정질 실리콘 층의 결정화 기술을 결정질 실리콘 태양전지 에미터 형성 공정에 적용하고자 한다. 이 때, 플라즈마화학증착 (Plasma-enhanced chemical vapor deposition, PECVD) 장비로 증착된 비정질 실리콘 층의 열처리를 통한 결정화 정도가 중요한 요소이다. 따라서, 비정질 실리콘 층의 결정화에 영향을 주는 인자에 대해 연구하였다. 비정질 실리콘 증착 조건(H2 가스 비율, 도펀트 유무), 실리콘 기판의 결정방향, 열처리 온도에 따른 결정화 정도를 엘립소미터(elipsometer), 투과전자현미경 (transmission electron microscope, TEM), 적외선 분광기 (Fourier Transform Infrared, FT-IR) 측정을 통하여 비교 하였다. 이를 기반으로 결정화 온도에 따른 비정질 실리콘의 결정화를 위한 활성화 에너지를 계산하였다. 비정질 실리콘 증착 조건 보다 기판의 결정방향이 결정화 정도에 크게 영향을 미치는 것으로 확인하였다.

• 한국재료학회지
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• 제27권2호
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• pp.107-112
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• 2017

The BCBJ (Back Contact and Back Junction) or back-lit solar cell design eliminates shading loss by placing the pn junction and metal electrode contacts all on one side that faces away from the sun. However, as the electron-hole generation sites now are located very far from the pn junction, loss by minority-carrier recombination can be a significant issue. Utilizing Medici, a 2-dimensional semiconductor device simulation tool, the interdependency between the substrate thickness and the minority-carrier recombination lifetime was studied in terms of how these factors affect the solar cell power output. Qualitatively speaking, the results indicate that a very high quality substrate with a long recombination lifetime is needed to maintain the maximum power generation. The quantitative value of the recombination lifetime of minority-carriers, i.e., electrons in p-type substrates, required in the BCBJ cell is about one order of magnitude longer than that in the front-lit cell, i.e., $5{\times}10^{-4}sec$ vs. $5{\times}10^{-5}sec$. Regardless of substrate thickness up to $150{\mu}m$, the power output in the BCBJ cell stays at nearly the maximum value of about $1.8{\times}10^{-2}W{\cdot}cm^{-2}$, or $18mW{\cdot}cm^{-2}$, as long as the recombination lifetime is $5{\times}10^{-4}s$ or longer. The output power, however, declines steeply to as low as $10mW{\cdot}cm^{-2}$ when the recombination lifetime becomes significantly shorter than $5{\times}10^{-4}sec$. Substrate thinning is found to be not as effective as in the front-lit case in stemming the decline in the output power. In view of these results, for BCBJ applications, the substrate needs to be only mono-crystalline Si of very high quality. This bars the use of poly-crystalline Si, which is gaining wider acceptance in standard front-lit solar cells.

• 한국재료학회지
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• 제17권2호
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• pp.73-80
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• 2007

For the sub-65 nm CMOS process, it is necessary to develop a new silicide material and an accompanying process that allows the silicide to maintain a low sheet resistance and to have an enhanced thermal stability, thus providing for a wider process window. In this study, we have evaluated the property and unit process compatibility of newly proposed composite silicides. We fabricated composite silicide layers on single crystal silicon from $10nm-Ni_{1-x}Co_x/single-crystalline-Si(100),\;10nm-Ni_{1-x}Co_x/poly-crystalline-\;Si(100)$ wafers (x=0.2, 0.5, and 0.8) with the purpose of mimicking the silicides on source and drain actives and gates. Both the film structures were prepared by thermal evaporation and silicidized by rapid thermal annealing (RTA) from $700^{\circ}C\;to\;1100^{\circ}C$ for 40 seconds. The sheet resistance, cross-sectional microstructure, surface composition, were investigated using a four-point probe, a field emission scanning probe microscope, a field ion beam, an X-ray diffractometer, and an Auger electron depth profi1ing spectroscopy, respectively. Finally, our newly proposed composite silicides had a stable resistance up to $1100^{\circ}C$ and maintained it below $20{\Omega}/Sg$., while the conventional NiSi was limited to $700^{\circ}C$. All our results imply that the composite silicide made from NiCo alloy films may be a possible candidate for 65 nm-CMOS devices.