• Journal of the Korean Society for Precision Engineering
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• v.15 no.1
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• pp.51-59
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• 1998

The purposes of the paper are to consider the failure phenomenon based on delamination and crack when the encapsulant of plastic IC package under hygrothermal loading in the IR soldering process is on elastic and viscoelastic behavior due to the temperature and to show the optimum design using fracture mechanics. The model for analysis is the plastic SOJ package with a dimpled diepad. The package model with the perfect delamination between chip and diepad is chosen to estimate the resistance to fracture by calculating J-integrals in low temperature and C(t)-integrals in high temperature with the change of the design under hygrothermal loading. The optimum design to depress the delamination and crack in the plastic IC package is presented.

• Journal of the Korean Society for Precision Engineering
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• v.15 no.1
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• pp.43-50
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• 1998

The purpose of the paper is to protect the damage of plastic IC package with searching the cause of the fracture due to the delamination and crack when the encapsulant of plastic IC package is on viscoelastic behavior with the effect of creep on high temperature, The model for analysis is the plastic SOJ package with dimpled diepad in the IR soldering process of surface mounting technology. The risk of delamination with calculating the distribution of viscoelastic thermal stress in the package without the crack in the surface mounting process is checked. The package model with the perfect delamination between chip and diepad is chosen to estimate the resistance against fracture in thermal loading with calculating C (t)-integrals according to the change of the design. The optimum design to depress the delamination and crack is presented.

• Journal of Mechanical Science and Technology
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• v.18 no.3
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• pp.357-369
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• 2004

The purposes of the paper are to analyze the fracture phenomenon by delamination and cracking when the encapsulant of plastic IC package with polyimide coating shows viscoelastic behavior under hygrothermal loading in the IR soldering process and to suggest more reliable design conditions by the approaches of stress analysis and fracture mechanics. The model is the plastic SOJ package with the polyimide coating surrounding chip and dimpled diepad. On the package without cracks, the optimum position and thickness of polyimide coating to decrease the maximum differences of strains at the bonding surfaces of parts of the package are studied. For the model delaminated fully between the chip and the dimpled diepad, C(t)-integral values are calculated for the various design variables. Finally, the optimal values of design variables to depress the delamination and crack growth in the plastic IC package are obtained.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.20 no.4
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• pp.1347-1355
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• 1996

The purpose of this paper is to evaluate the delamination and fracture integrity of the IC plastic package under hygrothermal loading by stress analysis and fracture mechanics approaches. The plastic SOJ package with a dimpled diepad under the reflow slodering process of IR heating type is considered. On the package without a crack, the stress variation according to the change of the design variables such as the material and shape of the package is calculated and the possibility of delamination is considered. For the model fully delaminated between the chip and diepad, J-integrals are calculated for the various design variables and the fracture integrity is discussed. From the results, optimal design values of variables to prevent the delamination and fracture of IC package are obtained. In this study, FDM program to obtain the vapor pressure from the content of moisture absorbed into the package is developed.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.6
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• pp.709-716
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• 2004

In order to prevent the interface delamination of an plastic IC package in the infrared (IR) soldering process, we tried to reduce stress by parameterization, sensitivity analysis and unconstraint optimization. The design variables of dimensions and material properties are determined among all the possible variables from the parametric study. Their optimized values are determined by applying the unconstraint optimization to the parameterized IC package. The maximum von-Mises stress value decreases greatly by optimum design.

• Electronics and Telecommunications Trends
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• v.4 no.4
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• pp.17-33
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• 1989

Hermetic 패키지는 재질 특성상 Plastic 패키지보다 환경내구성이 우수하고 수명이 긴 장점이 있으나, 가격이 높고 사용자의 주문에 의한 수작업으로 수급이 어려운 단점이 있다. 한편 Plastic 패키지는 가격이 낮고 수급이 용이한 반면 환경 특히 습기로 인한 고장으로 Hermetic 패키지보다 신뢰도가 낮아서 고신뢰도를 요구하는 군사용 및 산업용기기에서의 사용은 기피되어 왔다. 그러나 최근 Plastic 패키지의 단점을 개선하려는 노력으로 반도체칩의 수율 향상과 더불어 습기에 강한 재료가 개발되고 웨이퍼 제조기술이 발전됨에 따라 Plastic 패키지의 신뢰도가 향상되어 통신기기등 산업용 기기에까지 사용영역을 확대해 가고 있다. 또한 국내의 통신시장 개방에 따라 통신시스팀의 성능개선 및 신뢰성 제고를 통한 대외 경쟁력이 요구되어 통신시스팀에 Plastic 패키지 사용에 대한 인식이 증대하는 추세이다. 본고에서는 IC 패키지(Hermetic, Plastic)의 특성 및 성능을 비교 분석하고 이와 병행하여 Plastic 패키지의 최근 기술동향을 파악함으로써 통신시스팀에 사용하는 IC 패키지에 대한 고려사항을 제시하였다.

• Electrical & Electronic Materials
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• v.10 no.6
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• pp.519-527
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• 1997

The micro crack was occurred where the stress concentrated by the thermal stress which was induced during the cooling period after molding process or by the various reliability tests. In order to estimate the possibility of development from inside micro crack to outside fracture, the fracture toughness of EMC should be measured under the various applicable condition. But study was conducted very rarely for the above area. In order to provide a was to decide the fracture resistance of EMC (Epoxy Molding Compound) of plastic package which is produced by using transfer molding method, measuring fracture is studied. The specimens were made with various EMC material. The diverse combination of test conditions, such as different temperature, temperature /humidity conditions, different filler shapes, and post cure treatment, were tried to examine the effects of environmental condition on the fracture toughness. This study proposed a way which could improve the reliability of LOC(Lead On Chip) type package by comparing the measured $J_{IC}$ of EMC and the calculated J-integral value from FEM(Finite Element Method). The measured $K_{IC}$ value of EMC above glass transition temperature dropped sharply as the temperature increased. The $K_{IC}$ was observed to be higher before the post cure treatment than after the post cure treatment. The change of $J_{IC}$ was significant by time change. J-integral was calculated to have maximum value the angle of the direction of fracture at the lead tip was 0 degree in SOJ package and -30 degree in TSOP package. The results FEM simulation were well agreed with the results of measurement within 5% tolerance. The package crack was proved to be affected more by the structure than by the composing material of package. The structure and the composing material are the variables to reduce the package crack.ack.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.32-35
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• 2002

The work focuses on the development of a Cu lead-frame with a single-sided adhesive tape for cost reduction and reliability improvement of LOC (lead on chip) package products, which are widely used for the plastic-encapsulation of memory chips. Most of memory chips are assembled by the LOC packaging process where the top surface of the chip is directly attached to the area of the lead-frame with a double-sided adhesive tape. However, since the lower adhesive layer of the double-sided adhesive tape reveals the disparity in the coefficient of thermal expansion from the silicon chip by more than 20 times, it often causes thermal displacement-induced damage of the IC pattern on the active chip surface during the reliability test. So, in order to solve these problems, in the resent work, the double-sided adhesive tape is replaced by a single-sided adhesive tape. The single-sided adhesive tape does net include the lower adhesive layer but instead, uses adhesive materials, which are filled in clear holes of the base film, just for the attachment of the lead-frame to the top surface of the memory chip. Since thermal expansion of the adhesive materials can be accommodated by the base film, memory product packaged using the lead-flame with the single-sided adhesive tape is shown to have much improved reliability. Author allied this invention to the Korea Patent Office for a patent (4-2000-00097-9).

• Proceedings of the Materials Research Society of Korea Conference
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• 1995.11a
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• pp.3-3
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• 1995

Plastic IC encapsulation utilizing lead on chip(LOC) die attach technique allows higher device density per unit package area, and faster current speed and easter leadframe design. Nevertheless, since the top surface of the chip is directly attached to the area of the leadframe with a double-sided adhesive tape in the LOC package, it tends to be easily damaged by the leadframe, leading to limitation in its utilization. In this work, it is detailed how the damage of the chip surface occurs, and it is influenced and improved by the LOC construct.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.73-76
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• 2002

In this paper we present an integrated Hail sensor It for fan motors, fabricated in industrial bipolar process. As a discrete Hall sensor and signal processing circuitry In the fan motor system were Integrated into single chip a temperature dependence of Hall sensitivity and Hall offset voltage can be compensated and cancelled by on-chip circuitry. We Propose a novel temperature compensation of Hall sensitivity with negative temperature coefficient (TC) using the differential amplifier gain with Positive TC. After a package of the chip was sealed using a plastic Package 20 Pins, the thermal and magnetic characteristics were investigated. The obtained experimental results are in agreement with analytical predictions and have more excellent performance than\ulcorner conventional the fan motor system using discrete Hall sensor.