• ETRI Journal
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• v.42 no.3
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• pp.376-387
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• 2020

Massive computation of the reconstruction algorithm for compressive sensing (CS) has been a major concern for its real-time application. In this paper, we propose a novel high-speed architecture for the orthogonal matching pursuit (OMP) algorithm, which is the most frequently used to reconstruct compressively sensed signals. The proposed design offers a very high throughput and includes an innovative pipeline architecture and scheduling algorithm. Least-squares problem solving, which requires a huge amount of computations in the OMP, is implemented by using systolic arrays with four new processing elements. In addition, a distributed-arithmetic-based circuit for matrix multiplication is proposed to counterbalance the area overhead caused by the multi-stage pipelining. The results of logic synthesis show that the proposed design reconstructs signals nearly 19 times faster while occupying an only 1.06 times larger area than the existing designs for N = 256, M = 64, and m = 16, where N is the number of the original samples, M is the length of the measurement vector, and m is the sparsity level of the signal.

• Smart Structures and Systems
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• v.25 no.6
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• pp.733-749
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• 2020

This study presents a computer vision-based approach for representing time evolution of structural damages leveraging a database of inspection images. Spatially incoherent but temporally sorted archival images captured by robotic cameras are exploited to represent the damage evolution over a long period of time. An access to a sequence of time-stamped inspection data recording the damage growth dynamics is premised to this end. Identification of a structural defect in the most recent inspection data set triggers an exhaustive search into the images collected during the previous inspections looking for correspondences based on spatial proximity. This is followed by a view synthesis from multiple candidate images resulting in a single reconstruction for each inspection round. Cracks on concrete surface are used as a case study to demonstrate the feasibility of this approach. Once the chronology is established, the damage severity is quantified at various levels of time scale documenting its progression through time. The proposed scheme enables the prediction of damage severity at a future point in time providing a scope for preemptive measures against imminent structural failure. On the whole, it is believed that the present study will immensely benefit the structural inspectors by introducing the time dimension into the autonomous condition assessment pipeline.

• The Journal of Korea Robotics Society
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• v.14 no.1
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• pp.22-30
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• 2019

For effective human-robot interaction, robots need to understand the current situation context well, but also the robots need to transfer its understanding to the human participant in efficient way. The most convenient way to deliver robot's understanding to the human participant is that the robot expresses its understanding using voice and natural language. Recently, the artificial intelligence for video understanding and natural language process has been developed very rapidly especially based on deep learning. Thus, this paper proposes robot vision to audio description method using deep learning. The applied deep learning model is a pipeline of two deep learning models for generating natural language sentence from robot vision and generating voice from the generated natural language sentence. Also, we conduct the real robot experiment to show the effectiveness of our method in human-robot interaction.

• Journal of Korea Society of Industrial Information Systems
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• v.24 no.1
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• pp.31-38
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• 2019

In this paper, we develop a beamforming front end platform with pipeline circuit configuration method that can apply various clinical diagnostic applications of ultrasound image technology. Hardware design targets compression applications as well as scalable applications where power, integration levels and replication possibilities are important. Firmware design was implemented to achieve optimal FPGA parallel processing level by constructing new IP and system-oriented design environment to accelerate design productivity with maximum productivity improvement using Vivado HLS tool, which is a next generation high level synthesis tool. Former supports the high-speed management function of scan data that can create an image area arbitrarily and can be appropriately corrected and supplemented when reconfiguring or changing system specifications in the future.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.50-57
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• 2009

This paper proposes a VLSI architecture of CAVLC hardware decoder which is a tool eliminating statistical redundancy in H.264/AVC video compression. The previous CAVLC hardware decoder used four stages to decode five code symbols. The previous CAVLC hardware architectures decreased decoding performance because there was an unnecessary idle cycle in between state transitions. Likewise, the computation of valid bit length includes an unnecessary idle cycle. This paper proposes hardware architecture to eliminate the idle cycle efficiently. Two methods are applied to the architecture. One is a method which eliminates an unnecessary things of buffers storing decoded codes and then makes efficient pipeline architecture. The other one is a shifter control to simplify operations and controls in the process of calculating valid bit length. The experimental result shows that the proposed architecture needs only 89 cycle in average for one macroblock decoding. This architecture improves the performance by about 29% than previous designs. The synthesis result shows that the design achieves the maximum operating frequency at 140Mhz and the hardware cost is about 11.5K under a 0.18um CMOS process. Comparing with the previous design, it can achieve low-power operation because this design is implemented with high throughputs and low gate count.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.91-97
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• 2000

With the brilliant development of information communication and the rapid spread of internet, current network communication is carrying several up-to-date functions such as electronic commerce, activation of electro currency or electronic signature and will produce more advanced services in the future. Information communication network such as that electronic commerce would demand the more safe and transparent guard of network, and anticipate the more fast performance of network. In this paper, in order to meet the several demands, DES(data encryption standard) with parallel feistel structure, which feistel structure of the basic structure of DES is transformed into in parallel, is proposed. The existing feistel structure can't use pipeline method for the structural problem of DES itself-the propagation of error. therefore, this modified parallel feistel structure could improve largely the performance of DES which had to have the trade-off relation between data processing speed and data security and in addition a method proposed in SEED having adopted the modified parallel feistel structure shows more excellent secure function and/or fast processing ability. The used CAD Tool use Synopsys Ver. 1999. 10 in both of synthesis and simulation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.12
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• pp.513-519
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• 2002

This paper proposes a high-speed FFT processor for orthogonal frequency-division multiplexing(OFDM) systems. The Proposed architecture uses a single-memory architecture and uses a radix-4 algorithm for high speed. The proposed memory is partitioned into four banks for high-speed computation. It uses an in-place memory strategy that stores butterfly outputs in the same memory location used by butterfly inputs. Therefore, the memory size can be reduced. The SQNR of about 80dB is achieved with 20-bit input and 20-bit twiddle factors. The architecture has been modeled by VHDL and logic synthesis has been performed using the SamsungTM 0.5㎛ SOG cell library (KG80). The implemented FFT processor consists of 98,326 gates excluding memory. It has smaller hardware than existing pipeline FFT processors for more than 1024-point FFTs. The processor can operate at 42MHz and calculate a 256-point complex FFT in 6us. It satisfies tile required processing speed of 8.4㎲ in the HomePlug standard.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.2
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• pp.78-84
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• 2000

The Viterbi decoders can be classified into serial Viterbi decoders and parallel Viterbi decoders. Parallel Viterbi decoders can handle higher data rates than serial Viterbl decoders. This paper designs and implements a fully parallel Viterbi decoder for high speed multimedia communications. For high speed operations, the ACS (Add-Compare-Select) module consisting of 64 PEs (Processing Elements) can compute one stage in a clock. In addition, the systolic away structure with 32 pipeline stages is developed for the TB (traceback) module. The implemented Viterbi decoder can support code rates 1/2, 2/3, 3/4, 5/6 and 7/8 using punctured codes. We have developed Verilog HDL models and performed logic synthesis. The 0.6 ${\mu}{\textrm}{m}$ SAMSUNG KG75000 SOG cell library has been used. The implemented Viterbi decoder has about 100,400 gates, and is running at 70 MHz in the worst case simulation.

• Journal of Plant Biotechnology
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• v.47 no.3
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• pp.209-217
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• 2020

The presence of high amounts of seed storage proteins (SSPs) improves the overall quality of soybean seeds. However, these SSPs pose a major limitation due to their high abundance in soybean seeds. Although various technical advancements including mass-spectrometry and bioinformatics resources were reported, only limited information has been derived to date on soybean seeds at proteome level. Here, we applied a tandem mass tags (TMT)-based quantitative proteomic analysis to identify the significantly modulated proteins in the seeds of two soybean cultivars showing varying protein contents. This approach led to the identification of 5,678 proteins of which 13 and 1,133 proteins showed significant changes in Daewon (low-protein content cultivar) and Saedanbaek (high-protein content cultivar) respectively. Functional annotation revealed that proteins with increased abundance in Saedanbaek were mainly associated with the amino acid and protein metabolism involved in protein synthesis, folding, targeting, and degradation. Taken together, the results presented here provide a pipeline for soybean seed proteome analysis and contribute a better understanding of proteomic changes that may lead to alteration in the protein contents in soybean seeds.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.12A
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• pp.1311-1319
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• 2007

This paper presents the VHDL implementation procedure of the passive RFID tag operating in Ultra High Frequency. The operation of the tag compatible with the EPCglobal Class1 Generation2(GEN2) protocol is verified by timing simulation after synthesis and implementation. Due to the reading range with relatively large distance, a passive tag needs digital processor which facilitates faster decoding, encoding and state transition for enhancement of an interrogation rate. In order to satisfy linking time, the pipe-line structure is used, which can minimize latency to serial input data stream. We also propose the sampling strategy to decode the Preamble, the Frame-sync and PIE symbols in reader commands. The simulation results with the fastest data rate and multi tags environment scenario show that the VHDL implemented tag performs faster operation than GEN2 proposed.