• Transactions of the Korean Society of Mechanical Engineers A
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• v.40 no.1
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• pp.81-86
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• 2016

The valves used to control or shut off the flow through a pipeline can be divided into many different types, including gate valves, globe valves, and check valves. Globe valves, in particular, have excellent properties, and because they can easily control the flow under high-pressure conditions, they are generally used in LNG ship and steam pipelines. In this paper, a method for changing the shape of a seat was suggested to solve the valve leakage problem from a structural perspective. In addition, the stress distribution and directional deformation were compared for each model. The suggested models were thus validated, and the optimized seat structure, which includes a self-supporting capability for decreasing the amount of leakage, was determined.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.133-142
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• 2012

In this paper, we propose and implement a high-speed algorithm for CGH that is to calculate digital hologram by modeling the interference phenomenon for tow lights. This algorithm changes the computation equations into a parallel-computable ones and implements it with a structure consisting of two kinds of cells (initial calculation cell, and update calculation cell). The parallel computation algorithm is to get the rest hologram pixels concurrently after calculation the first hologram column. Here, the initial calculation cells compute the first column of the hologram and the update calculation cells compute the rest of the hologram. The two kinds of cells performs a pipeline operation to complete the operations of the two cells at the same time. A CGH calculator to compute the hole hologram for a light source is structured by arranging the two kinds of cells. Results from simulation showed that the maximum operation frequency is about 215MHz. So, experiments are performed by setting this frequency and the same environments as the method showing the best performance. As the results, the proposed one could complete the computation of 81.75 CGH frames per second, while the previous method computes 62.9 CGH frames per second.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.66-74
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• 2001

In this paper, we proposed the new structure of the Rake Finger using Walsh Switch, the shared accumulator, and the pipeline FWHT(Fast Walsh Hadamard Transform) algorithm for reducing the signal processing complexity resulting from the increase of the number of data correlators. The function simulation of the proposed architecture is performed by Synopsys tool and the timing simulation is performed by Compass tool. The number of computational operation in the proposed data correlators is 160 additions and the conventional ones is 512 additions when the number of walsh code channels is 4. As a result, it is reduced about 3.2 times other than the number of computational operation of the conventional ones. Also, the result shows that the data processing time of the proposed Rake Finger architecture is 90,496[ns] and the conventional ones is 110,696[ns]. It is 18.3% faster than the data processing time of the conventional Rake Finger architecture.

• The KIPS Transactions:PartA
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• v.12A no.3 s.93
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• pp.263-272
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• 2005

The addressing mode for data is performed by the software in yon Neumann-concept(SISD) computer a priori without hardware design of an address counter for operands. Therefore, in the addressing mode for the vector the corresponding variables as much as the number of the elements should be specified and used also in the software method. This is because not for operand but only for an instructions, quasi PC(program counter) is designed in hardware physically. A vector has a characteristic of a structural dimension. In this paper we propose to design a hardware unit physically external to the CPU for addressing only the elements of a vector unit with the structure and dimension. Because of the high speed performance for a vector processing it should be designed in the SIMD pipeline mechanics. The proposed mechanics is evaluated through a simulation. Our result shows $12\%$ to $30\%$ performance enhancement over CRAY architecture under the same hardware consideration(processing unit).

• Journal of the Korean Institute of Gas
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• v.24 no.5
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• pp.39-46
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• 2020

This paper is considered about centerline segregation of API 5L steel used in pipeline. Mn/S, Nb and C were known as segregated elements in the centerline of pipe thickness. The Mn usually was accompanied by S consisting of long viscous shape. Microstructure of the centerline was composed of MnS and Nb/Ti indusions including oxide. The segregation effect in centerline region was analyzed by OM, SEM/EDS and micro Vickers hardness. The Mn, Nb and C are retarded elements in transformation from austenite to ferrite or martensite. These elements could derive a bainitic microstructure as a kind of martensite, which is different from difference and element segregation between in matrix and centerline derived from steel melting and heat treatment.

• Environmental Engineering Research
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• v.16 no.3
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• pp.159-164
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• 2011

This study examined the emission characteristics of impure gas-like hydrogen sulfide and siloxane contained in landfill gas (LFG) and investigated the effect of impure gas on LFG utility facilities. As a result of an LFG component analysis from eight landfills in the same environment, hydrogen sulfide averaged 436 ppmv (22-1,211 ppmv), and the concentration of total siloxane averaged 7.95 mg/$m^3$ (1.85-21.18 mg/$m^3$). In case of siloxane concentration by component, the ratio of D4 (average 3.79 mg/$m^3$) and D5 (average 2.64 mg/$m^3$) indicated the highest level. Different kinds of scales were found on the gas air heater (GAH) and inside the boiler. The major component of scale from the GAH was $Fe_2O_3$ of 38.5%, and it was caused by hydrogen sulfide. Other scale was found on the bottom and the wall of the boiler and the scale was silicon dioxide of 92.8% and 98.9%. The silicon dioxide scale was caused by combustion of siloxane. As a result of a scanning electron microscopy analysis, the structure of the silicon dioxide scale from the boiler was an immediate filamentous type. Consequently, as silicon dioxide scale is bulky, such bad effects were worsening, as an interruption in heat conduction, increase in fuel consumption, damage to the boiler by overheating, and clogged emission pipeline could occur in LFG utility facilities.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.2
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• pp.78-84
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• 2000

The Viterbi decoders can be classified into serial Viterbi decoders and parallel Viterbi decoders. Parallel Viterbi decoders can handle higher data rates than serial Viterbl decoders. This paper designs and implements a fully parallel Viterbi decoder for high speed multimedia communications. For high speed operations, the ACS (Add-Compare-Select) module consisting of 64 PEs (Processing Elements) can compute one stage in a clock. In addition, the systolic away structure with 32 pipeline stages is developed for the TB (traceback) module. The implemented Viterbi decoder can support code rates 1/2, 2/3, 3/4, 5/6 and 7/8 using punctured codes. We have developed Verilog HDL models and performed logic synthesis. The 0.6 ${\mu}{\textrm}{m}$ SAMSUNG KG75000 SOG cell library has been used. The implemented Viterbi decoder has about 100,400 gates, and is running at 70 MHz in the worst case simulation.

• Journal of Ocean Engineering and Technology
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• v.24 no.1
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• pp.178-184
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• 2010

Today, there has been a decrease in international shipping because of the weakening in global economies. Therefore, shipowners are thinking more about Floating Production Storage and Offloading (FPSO), which can perform functions related to the transporting, storage, and tracking of crude oil from oil wells. Given the huge expense of these special ships, shipowners require workers who can solve problems quickly and secure sustainable production functions in this age of globalization. Furthermore, it is important to design, construct, and maintain facilities so that a ship remains in operation over a long term. This paper discusses a system that uses knowledge-based AR to help workers improve their understanding and deal with pipeline equipment problems safely. In addition, it displays a 3CAD model and status information for products to improve their recognition on the FPSO that they intend to inspect. At the same time, the system works quickly and offers solutions for dangerous circumstances or malfunctions. It thus helps to maintain the functionality of the FPSO throughout its life-cycle.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1433-1443
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• 1993

DCT(Discrete Cosine Transform) / IDCT(Inverse DCT) is widely used in various image compression and decompression systems as well as in DSP(Digital Signal Processing) applications. Since DCT/ IDCT is one of the most complicated part of the compression system, the performance of the system can be greatly enchanced by improving the speed of DCT/IDCT operation. In this thesis, we designed a DCT/IDCT core processor using module generator technique. By utilizing the partial sum and DA(Distributed Arithmetic) techniques, the DCT/ IDCT core processor is designed within small area. It is also designed to perform the IDCT(Inverse DCT) operation with little additional circuitry. The pipeline structure of the core processor enables the high performance, and the high accuracy of the DCT/IDCT operation is obtained by having fewer rounding stages. The proposed design is independent of design rules, and the number of the input bits and the accuracy of the internal calculation coa be easily adjusted due to the module generator technique. The accuracy of the processor satisfies the specifications in CCITT recommendation H, 261.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.10-17
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• 2011

As the data path of the processor widens and the depth of the pipeline deepens, the number of required registers increases. Consequently, careful attention must be paid to the design of clocked storage elements like latches and flipflops as they have a significant bearing on the overall performance of a synchronous VLSI circuit. As technology is also scaling down, noise immunity is becoming an important factor. In this paper, we present a new flipflop which has an improved noise immunity when compared to the hybrid latch flipflop and the conditional precharge flipflop. Simulation results in 65nm CMOS technology with 1.2V supply voltage are used to demonstrate the effectiveness of the proposed flipflop structure.