• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.2
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• pp.209-216
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• 2013

In this paper, we design and analyze digital retrodirective array antenna (RDA) system in 60GHz wireless communication for low power consumption and high quality. Digital RDA can automatically make beam toward source without information about the direction of incoming signal, this system is able to do low power communication thanks to increased signal to interference noise ratio (SINR) because making the beam toward source can reduce interference signals. The frequency offset seriously arises when millimetric wave band like 60GHz is used to communicate for high-speed transmission. The proposed system is robustly designed to frequency offset through designing digital phase lock loop in order to solve the problem of frequency offset. In this paper, we analyze the performance of the proposed system according to the number of array antenna and frequency offset. striking space.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.161-166
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• 1999

The global trends of mobile communication system is moving toward digitizing, high-speed and large-capacity. Also, to utilize the limited frequency-resource efficiently, spread spectrum system is a mainstream. In this study we are concerning with the fast frequency-hopping system. Instead of the PLL with many problems such as phase-noise, we used the DDS is popular in these days minimizes the disadvantage of PLL. In the case the FFH system is designed using the PLL, it is difficult to be satisfied of the design conditions such as RF badwidth and the settling time of PLL, and it has limitation because of complex circuit by using the balanced modulator. In this study, we evaluated the performance in order to design the FFH system using the DDS. The system that has the improvement of error rate, 1Mhps hopping rate and 5MHz RF bandwidth is designed and evaluated.

• Journal of Broadcast Engineering
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• v.10 no.1 s.26
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• pp.31-42
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• 2005

ATSC DTV system uses FPLL block for acquiring the frequency synchronization. Because the FPLL uses only the pilot signal, the frequency convergence range becomes narrower and it takes a more time to acquire the frequency synchronization as the pilot is distorted. And the spectrum shape around the pilot makes an asymmetric convergence range between the positive frequency offset and the negative frequency offset. This paper proposes the algorithm that requires the Installation of the fitters at the both edges of a VSB spectrum and uses the signal power that passes these filters. The proposed algorithm complements the problems of the asymmetric convergence range and overcomes the performance degradation due to the distortion of a pilot level.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.2
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• pp.152-159
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• 2019

In general, a Doppler radar can measure only the velocity of a moving target. To measure the distance of a moving target, it is necessary to use a frequency-modulated continuous wave or pulse radar. However, the latter are very complex in terms of both hardware as well as signal processing. Moreover, the requirement of wide bandwidth necessitates the use of millimeter-wave frequency bands of 24 GHz and 77 GHz. Recently, a new kind of Doppler radar using multitone frequency has been studied to sense the distance of moving targets in addition to their speed. In this study, we show that distance sensing of moving targets is possible by adjusting only the frequency of a 2.4 GHz Doppler radar with low cost phase lock loop. In particular, we show that distance can be sensed using only alternating current information without direct current offset information. The proposed technology satisfies the Korean local standard for low power radio equipment for moving target identification in the 2.4 GHz frequency band, and enables multiple long-range sensing and radio-frequency identification applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10C
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• pp.1032-1041
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• 2007

The global navigation satellite system (GNSS), which is the core technique for the location based service, adopts the direct sequence/spread spectrum (DS/SS) as its modulation method. The success of a DS/SS system depends on the synchronization between the received and locally generated pseudo noise (PN) signals. As a step in the synchronization process, the tacking scheme performs fine adjustment to bring the phase difference between the two PN signals to zero. The most widely used tracking scheme is the delay locked loop with early minus late discriminator (EL-DLL). In the ideal case, the EL-DLL is the best estimator among various DLL. However, in the band-limited multipath environment, the EL-DLL has tracking bias. In this paper, the timing offset range of correlation function is divided into advanced offset range (AOR) and delayed offset range (DOR) centering around the correct synchronization time point. The tracking bias results from the following two reasons: symmetry distortion between correlation values in AOR and DOR, and mismatch between the time point corresponding to the maximum correlation value and the synchronization time point. The former and latter are named as the type I and type II tracking bias, respectively. In this paper, when the receiver has finite bandwidth in the presence of multipath signals, it is shown that the type II tracking bias becomes a more dominant error factor than the type I tracking bias, and the correlation values in AOR are not almost changed. Exploiting these characteristics, we propose a novel tracking bias mitigation scheme and demonstrate that the tracking accuracy of the proposed scheme is higher than that of the conventional scheme, both in the presence and absence of noise.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.505-511
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• 2008

The global navigation satellite system (GNSS) is using a direct sequence/spread spectrum (DS/SS) modulation. In order to recover the information data, the DS/SS system first performs a two-step synchronization process: acquisition and tracking. The acquisition process adjusts the phase difference between the received and locally generated acquisition sequences within ${\pm}T_c/2$ or less, where $T_c$ is the chip period. The tracking process performs fine synchronization. In this paper, we focus on the tracking issue. The single delta delay locked loop($\Delta$-DLL) is the optimal tracking scheme for a GNSS in the absence of multipath signals, where $\Delta$ means the spacing between the early and late correlation time offset. In the multipath environments, however, the $\Delta$-DLL suffers from huge estimation bias(denoted by $\beta$) caused by distorted correlation values. Although some modified schemes such as a $\Delta$-DLL with a narrow $\Delta$ and a double delta DLL (${\Delta}^{(2)}$-DLL) were proposed to reduce the estimation bias, they cannot remove the estimation bias completely and need more accurate acquisition process. This paper proposes a novel tracking scheme that can dramatically reduce the estimation bias, using the maximum slope change among the correlation outputs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.80-87
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• 2006

SONY corporation preoccupies $80\%$ of a market of the CCD used in a CCTV system. The CCD of SONY have high duality which can not follow the progress of capability. But there are some problems which differ the clock frequency used in CCD from the frequency used in common video encoder. To get the result by using common video encoder, the system needs a scaler that could adjust image size and PLL that synchronizes CCD's with encoder's clock So, this paper proposes the video encoder that is activated at equal clock used in CCD without scaler and PLL. The encoder converts ITU-R BT.601 4:2:2 or ITU-R BT.656 inputs from various video sources into NTSC or PAL signals in CVBS. Due to variable clock, property of filters used in the encoder is automatically changed by clock and filters adopt multiplier-free structures to reduce hardware complexity. The hardware bit width of programmable digital filters for luminance and chrominance signals, along with other operating blocks, are carefully determined to produce hish-quality digital video signals of ${\pm}1$ LSB error or less. The proposed encoder is experimentally demonstrated by using the Altera Stratix EP1S80B953C6ES device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.