• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.451-454
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• 2011

In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350MHz, and a VCO frequency is 270MHz. The lock time of clock generator is less then 3us at input reference frequency, 67.5MHz. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1mW at 1.8V supply and layout area is $0.384mm^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.2
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• pp.209-216
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• 2013

In this paper, we design and analyze digital retrodirective array antenna (RDA) system in 60GHz wireless communication for low power consumption and high quality. Digital RDA can automatically make beam toward source without information about the direction of incoming signal, this system is able to do low power communication thanks to increased signal to interference noise ratio (SINR) because making the beam toward source can reduce interference signals. The frequency offset seriously arises when millimetric wave band like 60GHz is used to communicate for high-speed transmission. The proposed system is robustly designed to frequency offset through designing digital phase lock loop in order to solve the problem of frequency offset. In this paper, we analyze the performance of the proposed system according to the number of array antenna and frequency offset. striking space.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.673-675
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• 2004

This study proposes controller with voltage-compensated drivers for producing gray-scaled pictures on passive matrix organic light emitting diodes (PMOLEDs) panels. The controller includes voltage type drivers so the output impedance of the driver is far less than that of the current-type driver. Its low output impedance provides better electron-optical properties than those of traditional current drivers. A free running clock and a group of counters are applied to the gray-scaled function so that phase lock loop (PLL) circuit can be reduced in the controller. A pre-charge function is used to enhance performance of the luminance of an active OLED pixel. As a result, distribution of the low gray level portion is achieved linear relationship with input data. In this work, the digital part of the proposed controller is implemented using FPGA chips, and analog parts are combined with a digital-analog converter (DAC) and analog switches. A still image is displayed on a $48^{\ast}64$ PMOLEDs panel to assess the luminance performance fir the controller. Based on its cost requirement and luminance performance, the controller is qualified to join the market for driving PMOLEDs panels.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.423-429
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• 2007

The clock recovery module of gap filler for satellite DMB is proposed. Proposed module sustains the output frequency of 10 MHz whether the received signal from the satellite is unstable or cut off within 0.5 sec. The advantages of this module is without frequency tuning at regular interval and low material cost. This module is fabricated by using CPLD as clock recovery IC and new type of loop filter for satisfying the fast lock time and long hold over time simultaneously. The measured performance of the fabricated module has a holdover time of 11 sec at frequency stability less than 0.01 ppm, and phase noise of -113 dBc/Hz at 100 Hz offset.

• Journal of Power Electronics
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• v.18 no.1
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• pp.234-250
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• 2018

This paper presents a new load sharing control for use between paralleled three-phase inverters in an islanded microgrid based on the online line impedance estimation by the use of a Kalman filter. In this study, the mismatch of power sharing when the line impedance changes due to temperature, frequency, significant differences in line parameters and the requirements of the Plug-and-Play mode for inverters connected to a microgrid has been solved. In addition, this paper also presents a new droop control method working with the line impedance that is different from the traditional droop algorithm when the line impedance is assumed to be pure resistance or pure inductance. In this paper, the line impedance estimation for parallel inverters uses the minimum square method combined with a Kalman filter. In addition, the secondary control loops are designed to restore the voltage amplitude and frequency of a microgrid by using a combined nominal value SOGI-PLL with a generalized integral block and phase lock loop to monitor the exact voltage magnitude and frequency phase at the PCC. A control model has been simulated in Matlab/Simulink with three voltage source inverters connected in parallel for different ratios of power sharing. The simulation results demonstrate the accuracy of the proposed control method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.80-87
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• 2006

SONY corporation preoccupies $80\%$ of a market of the CCD used in a CCTV system. The CCD of SONY have high duality which can not follow the progress of capability. But there are some problems which differ the clock frequency used in CCD from the frequency used in common video encoder. To get the result by using common video encoder, the system needs a scaler that could adjust image size and PLL that synchronizes CCD's with encoder's clock So, this paper proposes the video encoder that is activated at equal clock used in CCD without scaler and PLL. The encoder converts ITU-R BT.601 4:2:2 or ITU-R BT.656 inputs from various video sources into NTSC or PAL signals in CVBS. Due to variable clock, property of filters used in the encoder is automatically changed by clock and filters adopt multiplier-free structures to reduce hardware complexity. The hardware bit width of programmable digital filters for luminance and chrominance signals, along with other operating blocks, are carefully determined to produce hish-quality digital video signals of ${\pm}1$ LSB error or less. The proposed encoder is experimentally demonstrated by using the Altera Stratix EP1S80B953C6ES device.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.2
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• pp.152-159
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• 2019

In general, a Doppler radar can measure only the velocity of a moving target. To measure the distance of a moving target, it is necessary to use a frequency-modulated continuous wave or pulse radar. However, the latter are very complex in terms of both hardware as well as signal processing. Moreover, the requirement of wide bandwidth necessitates the use of millimeter-wave frequency bands of 24 GHz and 77 GHz. Recently, a new kind of Doppler radar using multitone frequency has been studied to sense the distance of moving targets in addition to their speed. In this study, we show that distance sensing of moving targets is possible by adjusting only the frequency of a 2.4 GHz Doppler radar with low cost phase lock loop. In particular, we show that distance can be sensed using only alternating current information without direct current offset information. The proposed technology satisfies the Korean local standard for low power radio equipment for moving target identification in the 2.4 GHz frequency band, and enables multiple long-range sensing and radio-frequency identification applications.