• IMMUNE NETWORK
• /
• v.11 no.5
• /
• pp.258-267
• /
• 2011

Background: Current management strategies attempt to diagnose rheumatoid arthritis (RA) at an early stage. Transcription profiling is applied in the search for biomarkers for detecting early-stage disease. Even though gene profiling has been reported using several animal models of RA, most studies were performed after the development of active arthritis, and conducted only on the peripheral blood and joint. Therefore, we investigated gene expression during the initial phase of collagen-induced arthritis (CIA) before the arthritic features developed in the thymus in addition to the peripheral blood and synovium. Methods: For gene expression analysis using cDNA microarray technology, samples of thymus, blood, and synovium were collected from CIA, rats immunized only with type II collagen (Cll), rats immunized only with adjuvant, and unimmunized rats on days 4 and 9 after the first immunization. Arrays were scanned with an Illumina bead array. Results: Of the 21,910 genes in the array, 1,243 genes were differentially expressed at least 2-fold change in various organs of CIA compared to controls. Among the 1,243 genes, 8 encode T-cell receptors (TCRs), including CD3${\zeta}$, CD3${\delta}$, CD3${\varepsilon}$, CD8${\alpha}$, and CD8${\beta}$ genes, which were down-regulated in CIA. The synovium was the organ in which the genes were differentially expressed between CIA and control group, and no difference were found in the thymus and blood. Further, we determined that the differential expression was affected by adjuvant more than Cll. The differential expression of genes as revealed by real-time RT-PCR, was in agreement with the microarray data. Conclusion: This study provides evidence that the genes encoding TCRs including CD3${\zeta}$, CD3${\delta}$, CD3${\varepsilon}$, CD8${\alpha}$, and CD8${\beta}$ genes were down-regulated during the initial phase of CIA in the synovium of CIA. In addition, adjuvant played a greater role in the down-regulation of the CD3 complex compared to CII. Therefore, the down-regulation of TCR gene expression occurred dominantly by adjuvant could be involved in the pathogenesis of the early stage at CIA.

• Journal of Navigation and Port Research
• /
• v.36 no.9
• /
• pp.715-720
• /
• 2012

This paper is to introduce the development of a LCD monitor-based pilots' ship handling simulator installed in the office of Korea Maritime Pilots Association. This simulator is composed of hardware which includes working server array, operation PC, monitor array, rudder, thruster and telegraph peripheral devices, and software which includes ship mathematical model software, ship conning software, image supporting software and so on. In this simulator, MMG mathematical model is used to create thirteen(13) ship models, which are based on sea trial data & pilots' opinion. According to requirements of pilots, virtual scenes of different port areas are built, and some required additional functions are also developed. By using this simulator, pilots can fulfill all kinds of training exercises, design of channel approaching ports, traffic safety analysis, prevention of accident research and other tasks, so as to grasp the characteristics of different ships, and accumulate experience for piloting.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.13 no.1
• /
• pp.8-16
• /
• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-㎛ column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970×10 ㎛2 and 248 ㎼, respectively.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.2
• /
• pp.184-188
• /
• 2014

There is a trade-off between read stability and writability under a full-/half-select condition in static random access memory (SRAM). Another trade-off in the minimum operating voltage between the read and write operation also exists. A new peripheral circuit for SRAM arrays, called a variation sensor, is demonstrated here to balance the read/write margins (i.e., to optimize the read/write trade-off) as well as to lower the minimum operation voltage for both read and write operations. A test chip is fabricated using an industrial 45-nm bulk complementary metal oxide semiconductor (CMOS) process to demonstrate the operation of the variation sensor. With the variation sensor, the word-line voltage is optimized to minimize the trade-off between read stability and writability ($V_{WL,OPT}=1.055V$) as well as to lower the minimum operating voltage for the read and write operations simultaneously ($V_{MIN,READ}=0.58V$, $V_{MIN,WRITE}=0.82V$ for supply voltage $(V_{DD})=1.1V$).

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.847-850
• /
• 2003

An Eye Ball Sensor (EBS) is a system that locates the point where the user gazes on. The conventional EBS using a CCD camera needs many peripherals, software computation causing high cost and power consumption. This paper proposes a compact EBS using smart CMOS Image Sensor (CIS) pixels. The proposed single chip EBS does not need any peripheral and operates at higher speed and lower cost than the conventional EBS. The test chip was designed and fabricated for 32$\times$32 smart CIS pixel array with a 0.35 um CMOS process occupying 5.3$\textrm{mm}^2$ silicon area.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.1141-1144
• /
• 2003

For proper communication with various types of IC-Card, multiple IC-Card interface complying with the IC-Card standard (ISO7816) is embedded and realized as a peripheral on the 32-bit RISC based system-on-a-chip. It provides the generation of either 3.3V or 5V power supply for the operation of the inserted IC-Card as well. IC-Card interface is divided into an analog front-end (AFE) and a digital back-end (DBE). The embedded DC-DC converters suitable for driving IC-Cards are incorporated in the AFE. The chip design for multiple IC-Card interface is implemented on a standard 0.35${\mu}{\textrm}{m}$ triple-metal double-poly CMOS process and is packaged in a 352-pin plastic ball grid array (PBGA). The total gate count is about 400,000, excluding the internal memory. Die area is 7890${\mu}{\textrm}{m}$ $\times$ 7890${\mu}{\textrm}{m}$.

• Journal of Power Electronics
• /
• v.12 no.6
• /
• pp.974-981
• /
• 2012

A FPGA based delta modulated single phase matrix converter has been developed that may be used in both cyclo-converters and cyclo-inverters. This converter is ideal for variable speed electrical drives, induction heating, fluorescent lighting, ballasts and high frequency power supplies. The peripheral input-output and FPGA interfacing have been developed through Xilinx 9.2i, to generate delta modulated trigger pulses for the converter. The controller has been relieved of the time consuming computational task of PWM signal generation by implementing the method of trigger pulse generation in a FPGA by using Hardware Description Language VHDL in Xilinx. The trigger circuit has been tested qualitatively by observing various waveforms on an oscilloscope. The operation of the proposed system has been found to be satisfactory.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.2
• /
• pp.24-30
• /
• 2009

In this paper, the FPGA modem platform complying with 3GPP Release 7 eHSPA specifications and its regularized verification flow are proposed. The FFGA platform consists of modem board supporting physical layer requirements, MCU and DSP core embedded control board to drive the modem board, and peripheral boards for RF interfacing and various equipment interfaces. On the other hand, the proposed verification flow has been regularized into three categories according to the correlation degrees of hardware-software inter-operation, such as simple function test, scenario test call processing and system-level performance test. When it comes to real implementations, the emulation verification strategy for low power mobile SoC is also introduced.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.9
• /
• pp.2109-2116
• /
• 2014

This paper presents the implementation and design of the advanced WI-FI systems with beam-forming antenna that radiate their power to the direction of user equipment to improve the overall throughput, contrast to the general WI-FI systems equipped with omni-antenna. The system consists of patch array antenna, DSP, FPGA, and Qualcomm's commercial chip. The beam-forming system on the FPGA utilizes the packet information from Qualcomm's commercial chip to control the phase shifters and attenuators of the patch array antenna. The PCI express interface has been used to maximize the communication speed between DSP and FPGA. The directions of arrival of users are managed using the database, and each user is distinguished by the MAC address given from the packet information. When the system wants to transmit a packet to one user, it forms beams to the direction of arrival of the corresponding user stored in the database to maximize the throughput. Directions of arrival of users are estimated using the received preamble in the packet to make its SINR as high as possible. The proposed beam-forming system was implemented using an FPGA and Qualcommm's commercial chip together. The implemented system showed considerable throughput improvement over the existing general AP system with omni-directional antenna in the multi-user communication environment.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2000.04a
• /
• pp.43-55
• /
• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology. Flip chip technology eliminates the need for wire bonding by redistributing the bond pads over the entire surface of the die. Instead of wires, the die is attached to the substrate utilizing a direct solder connection. Although several steps and processes are eliminated when utilizing flip chip technology, there are several new problems that must be overcome. The main issue is the mismatch in the coefficient of thermal expansion (CTE) of the silicon die and the substrate. This mismatch will cause premature solder Joint failure. This issue can be compensated for by the use of an underfill material between the die and the substrate. Underfill helps to extend the working life of the device by providing environmental protection and structural integrity. Flux residues may interfere with the flow of underfill encapsulants causing gross solder voids and premature failure of the solder connection. Furthermore, flux residues may chemically react with the underfill polymer causing a change in its mechanical and thermal properties. As flip chip packages decrease in size, cleaning becomes more challenging. While package size continues to decrease, the total number of 1/0 continue to increase. As the I/O increases, the array density of the package increases and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing. This paper will present the keys to successful flip chip cleaning processes. Process parameters such as time, temperature, solvency, and impingement energy required for successful cleaning will be addressed. Flip chip packages will be cleaned and subjected to JEDEC level 3 testing, followed by accelerated stress testing. The devices will then be analyzed using acoustic microscopy and the results and conclusions reported.