• 한국자동차공학회논문집
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• 제11권4호
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• pp.180-188
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• 2003

The vehicle simulator is a useful virtual reality system. The simulator enables engineers to effectively research and analyze various experiments. Therefore, the development of a specific vehicle simulator is required, and its performance must be verified. This paper verifies the performance of Pusan National University Vehicle Simulator. Human sensibility ergonomic tests of vehicle simulator were also executed. The sense of simulator motion was chosen as the standard of performance evaluation. The driver's senses were subdivided into senses of rectilinear and rotational velocities. This study extracted ergonomic sensibility words that can be used to evaluate the performance of the simulator As a practical application of simulator, the relation was studied between the sense of simulator motion and the characteristics of drivers, who are classified into their sexes and driving careers. A statistical method was applied to human sensibility ergonomic tests of vehicle simulator.

• 한국군사과학기술학회지
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• 제12권4호
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• pp.407-414
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• 2009

This paper describes a conceptual model for the performance analysis simulator of a weapon launching system. The system performance analysis simulator is envisioned to provide an integrated analysis environment in which the system performance and operational effectiveness can be analyzed in more rapid and efficient way. The conceptual model for the simulator describes a referent independently of specific technology and implementation, and it can be used to transform the simulator requirements into the simulator system specifications.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2005년도 종합학술발표회 논문집 Vol.15 No.1
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• pp.33-38
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• 2005

In this paper, a simulator for radar performance evaluation in a far-field test range is proposed, which can forecast maximum detection range, minimum detection range, number of test trials, resolution (range, azimuth, elevation) with input parameters before radar performance test and process results after. The proposed simulator is designed by Microsoft Foundation Class (MFC) of VC++ 6.0.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2003년도 추계학술대회 논문집(III)
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• pp.659-665
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• 2003

This paper presents a Train Communication Network simulator (TCNS) that can be used to evaluate the performance of TCN. TCN was accepted as the standard of the protocol for the communication network in trains. We carry out some simulation tests using the TCNS to show practical uses of the simulator. Results of some simulation tests are also reported. This paper presents a Train Communication Network simulator(TCNS) that can be used to evaluate the performance of TCN. TCN was accepted as the standard of the protocol for the communication network in trains. TCN of fieldbus was adopted as international standardization IEC 61375 in 1999. It has been operating on G7 train in korea. This paper developed TCNS(Train Communication Network simulator) as a simulator for performance evaluation. We can verify TCNS for preventing many kinds of occurring problems between the devices in data-communication. This study was developed TCNS as a simulator for the performance evaluation. We analyzed correlation between token, transmission data per paket and transmission speed of bus, through the TCNS, also analyzed result according to error rate of TCN. We carry out some simulation tests using the TCNS to show practical uses of the simulator. Results of some simulation tests are also reported.

• 한국시뮬레이션학회논문지
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• 제3권1호
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• pp.29-42
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• 1994

The architecture of a MIMD-type parallel computer system is specified: a simulator is developed to support design and evaluation of systems based on the architecture: and conducted with the simulator to evaluate system performance. The horizontal/vertical-bus(H/V-bus) system architecture provides an NxN array of processing elements which communicate with each other through a network of N horizontal buses and N vertical buses. The simulator, written in SLAM II and FORTRAN, is designed to provide high-resolution in simulating the IPC mechanism. Parameters provide the user with independent control of system size, PE speed and IPC mechanism speed. Results generated by the simulator include execution times, PE utilizations, queue lengths, and other data. The simulator is used to study system performance when a partial differential equation is solved by parallel Gauss-Seidel method. For comparisons, the benchmark is also executed on a single-bus system simulator that is derived from the H/V-bus system simulator. The benchmark is also solved on a single PE to obtain data for computing speedups. An extensive analysis of results is presented.

• Journal of Power Electronics
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• 제5권4호
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• pp.319-328
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• 2005

This paper deals with the development of a new type of simulator for the study of the dynamic performance of an HVDC scheme. The new simulator uses a digital model of the power equipment and an analogue model of the existing HVDC controller. This simulator is used to study the dynamic performance of the Cheju - Haenam HVDC system and to verify the control characteristics of the HVDC system. The paper discusses the simulator development requirements and criteria. The paper provides guidelines for the development of the simulator and presents the results of the simulation studies.

• 한국생산제조학회지
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• 제24권5호
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• pp.541-547
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• 2015

In this study, the performance of a low-floor midsize bus under development is predicted through simulations. To predict the vehicle's acceleration, maximum speed, and uphill driving performance, a forward simulator which calculates the vehicle power is developed. Also we verify the forward simulator by comparing simulations and test result for benchmarking vehicle. To predict the fuel consumption, we use a backward simulator for a specified road cycle. However, to predict the fuel consumption using the backward simulation the engine fuel-consumption map is needed. The engine fuel-consumption map extracting data from a similar sized diesel engine is used by re-scaling the maximum torque. As a result, we simulate the vehicle's forward performance with a new engine. Further, we simulated the backward performance to optimize the fuel efficiency and gearshift timing.

• 전기학회논문지
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• 제59권2호
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• pp.267-271
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• 2010

Photovoltaic system simulator is under being developed for the performance test of Power conditioning system (PCS). The photovoltaic system simulator is required to emulate real system, which can be obtained by fast response controller. In this paper, we suggest a robust control method as a tool to design the simulator controller. The performance of the controller is determined by weighting functions, sensitivity function $W_1$ complementary sensitiviey function $W_3$, and a control signal shaping function $W_u$. Experimental results show that robust control method is promising for obtaining better performance of the photovoltaic system simulator.

• 반도체디스플레이기술학회지
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• 제22권3호
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• pp.78-83
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• 2023

This paper proposes a lightweight trace-driven Processing-In-Memory (PIM) simulator, TP-Sim. TP-Sim is a General Purpose PIM (GP-PIM) simulator that evaluates various PIM system performance-related metrics. Based on instruction and memory traces extracted from the Intel Pin tool, TP-Sim can replay trace files for multiple models of PIM architectures to compare its performance. To verify the availability of TP-Sim, we estimated three different system configurations on the STREAM benchmark. Compared to the traditional Host CPU-only systems with conventional memory hierarchy, simple GP-PIM architecture achieved better performance; even the Host CPU has the same number of in-order cores. For further study, we also extend TP-Sim as a part of a heterogeneous system simulator that contains CPU, GPGPU, and PIM as its primary and co-processors.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.408-411
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• 1999

Microarchitecture simulator is an important tool to verify and optimize the microarchitecture of a new microprocessor. Moreover. it can be use as a performance simulator to estimate the target microprocessor′s performance. And system software designers can use it as a software developing environment. This paper describes a "microarchitecture simulator for on-chip Multiprocessor microprocessor". It is a program-driven and cycle-based simulator that can execute simultaneous mutithreading benchmarks. We verified the microarchitecture of a new on-chip multiprocessor microprocessor with it and did performance simulations to estimate the performance of the on-chip multiprocessor microprocessor.