• Korean Journal of Materials Research
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• v.15 no.3
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• pp.202-208
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• 2005

The surface states of gate dielectrics affect device performance severely in Pentacene OTFTs. We have fabricated organic thin-film transistors (OTFTs) using pentacene as an active layer with chemically modified $SiO_2$ gate dielectrics. The effects of the surface treatment of $SiO_2$ on the electric characteristics of OTFTS were investigated. The surface of $SiO_2$ gate dielectric was treated by normal wet cleaning process, $O_2-plasma$ treatment, hexamethyldisilazane (HMDS), and octadecyltrichlorosilane (OTS) treatment. After the surface treatments, the contact angles and surface free energies were measured in order to analyze the surface state changes. In the electrical measurements, typical I-V characteristics of TFTs were observed. The field effect mobility, $\mu$, was calculated to be $0.29\;cm^2V^{-1}s^{-1}$ for OTS treated sample while those for the HMDS, $O_2$ plasma treated, and wet-cleaned samples were 0.16, 0.1, and $0.04\;cm^2V^{-1}s^{-1}$, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.08a
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• pp.342-342
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• 2009

• Proceedings of the Korean Vacuum Society Conference
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• 2009.02a
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• pp.271.1-271.1
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• 2009

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.445-448
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• 2006

Bias stress effect in pentacene organic thin-flim transistors with cross-linked PVA gate dielectric is analyzed. For negative gate bias stress, positive threshold voltage shift is observed. The injected charges from the gate electrode to the defect states of gate dielectric are regarded as the main origin of $V_T$ shift. The reduced bias stress effect using $SiO_2$ blocking layer confirms the assumed mechanism. It is also demonstrated that the inverter with $SiO_2$ blocking layer shows the negligible hysteresis owing to the reduced bias stress effect.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1364-1369
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• 2005

In this paper, we have identified the mechanism of C-V hysteresis behavior often observed in pentacene organic thin-film transistors (OTFTs). The capacitance-voltage (C-V) characteristics were measured for pentacene OTFTs fabricated on glass substrates with MoW as gate/source/drain electrode and TEOS $SiO_2$ as gate insulator. The measurements were made at room temperature and elevated temperatures. From the room temperature measurements, we found that the hysteresis behavior was caused by hole injection into the gate insulator from the pentacene semiconductor for large negative gate voltages, resulting in the negative flat-band voltage shift. However electron injection was observed only at elevated temperatures

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1291-1293
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• 2005

Hybrid insulator pentacene thin film transistors (TFTs) were fabricated with thermally grown oxide and cross-linked polyvinylalcohol (PVA) including surface treatment by dilute ploymethylmethacrylate (PMMA) layers on $n^+$ doped silicon wafer. Through the optimization of $SiO_2$ layer thickness in hybrid insulator structure, carrier mobility was increased to above 35 times than that of the TFT only with the gate insulator of $SiO_2$ at the same transverse electric field. The carrier mobility of 1.80 $cm^2$/V-s, subthreshold swing of 1.81 V/decade, and $I_{on}$/ $I_{off}$ current ratio > 1.10 × $10^5$ were obtained at low bias (less than -30 V) condition. The result is one of the best reported performances of pentacne TFTs with hybrid insulator including cross-linked PVA material at low voltage operation.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.380-380
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• 2013

본 논문에서는 외기 환경 요인 중에서 H2O와 O2의 영향으로 성능이 저하되는 유기박막트랜지스터(OTFT)의 수명시간 향상을 위하여 필요한 passivation layer의 효과에 대하여 알아 보았다. OTFT에 기존의 액상 공정이나 증착 공정으로 단일 passivation layer또는 다층 passivation layer를 형성하는 방식과는 다르게 향후에 산업 전반에 적용이 기대되는 것을 고려하여 제작 공정의 간편성을 위하여 film 형태로 되어 있는 열경화성 epoxy resin film으로 passivation layer를 구현하는 방법을 사용하여 OTFT의 storage stability를 평가하였다. passivation layer가 없는 OTFT와 열경화성 epoxy resin film으로 passivation된 OTFT의 전기적 특성이 서로 비교 평가되었으며 또한 30일 동안 온도 $25^{\circ}C$ 상대습도 40%의 환경을 갖는 Desicator 안에서 소자를 보관하여 시간에 따른 전기적 특성 변화를 검증하여 epoxy resin film의 passivation layer으로의 적용가능성을 검증하였다. 결과적으로 30일 후의 passivation layer가 없는 OTFT의 전기적 특성은 매우 낮게 떨어진 반면에 epoxy resin film으로 passivation layer가 구현된 OTFT의 mobility는 $0.060cm^2$/Vs, VT는 -0.18 V, on/off ratio는 $3.7{\times}10^3$으로 초기의 소자 특성이 잘 유지되는 결과를 얻었다. OTFT는 Flexible한 polyethersulfone (PES)기판에 게이트 전극이 하부에 있는 Bottom gate 구조로 제작되었고 채널 형성을 위한 유기반도체 재료로 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene이 사용되었고 spin coating된 Poly-4-vinylphenol (PVP)가 게이트 절연체로 사용되었다. 이때 Au전극은 Shadow mask를 이용하여 증착하였다. 또한 OTFT의 채널 길이 $100{\mu}m$, 채널 폭 $300{\mu}m$의 영역에 Drop casting법을 사용하여 채널을 형성하였다. 물리적 특성은 scanning electron microscopy (SEM), scanning probe microscopy (SPM), x-ray diffraction (XRD)를 사용하여 분석하였고, 전기적 특성은 Keithley-4200을 사용하여 추출하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.264-264
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• 2008

We fabricated a pentacene thin-film transistor with a Polymer/$SiO_2$ Double Gate Dielectrics and obtained a device with better electrical characteristics. This device was found to have a field-effect mobility of $0.04cm^2$/Vs, a threshold voltage of -2V, an subthreshold slope of 1.3 V/decade, and an on/off current ratio of $10^7$.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1216-1219
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• 2007

We have been developing printed organic TFTs for flexible displays. In this study, we have pay attention to the operation stability improvement of the organic TFTs, and studied several factors especially depending on the dielectric layers. From the detailed analysis of the effects of dielectric layers, we have proposed a new printed dielectric layer which is mainly consisting of metal oxide and gives high operation stability

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.221-221
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• 2013

Striving to replace the well known silicon nanocrystals embedded in oxides with solution-processable charge-trapping materials has been debated because of large scale and cost effective demands. Herein, a silicon quantum dot-polystyrene nanocomposite (SiQD-PS NC) was synthesized by postfunctionalization of hydrogen-terminated silicon quantum dots (H-SiQDs) with styrene using a thermally induced surface-initiated polymerization approach. The NC contains two miscible components: PS and SiQD@PS, which respectively are polystyrene and polystyrene chains-capped SiQDs. Spin-coated films of the nanocomposite on various substrate were thermally annealed at different temperatures and subsequently used to construct metal-insulator-semiconductor (MIS) devices and thin film field effect transistors (TFTs) having a structure p-$S^{++}$/$SiO_2$/NC/pentacene/Au source-drain. C-V curves obtained from the MIS devices exhibit a well-defined counterclockwise hysteresis with negative fat band shifts, which was stable over a wide range of curing temperature ($50{\sim}250^{\circ}C$. The positive charge trapping capability of the NC originates from the spherical potential well structure of the SiQD@PS component while the strong chemical bonding between SiQDs and polystyrene chains accounts for the thermal stability of the charge trapping property. The transfer curve of the transistor was controllably shifted to the negative direction by chaining applied gate voltage. Thereby, this newly synthesized and solution processable SiQD-PS nanocomposite is applicable as charge trapping materials for TFT based memory devices.