• Journal of Broadcast Engineering
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• v.16 no.6
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• pp.986-995
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• 2011

In this paper, we propose a noise whitening decision feedback equalizer for single carrier frequency division multiple access (SC-FDMA) receivers. SC-FDMA has the same advantage as that of orthogonal frequency division multiple access (OFDMA) in which the multipath effect can be removed easily, and also solves the problem of high peak to average power ratio (PAPR) which is the main drawback of OFDMA. Although SC-FDMA is a single carrier transmission scheme, a simple frequency domain linear equalizer (FD-LE) can be implemented as in OFDMA, which can dramatically reduce the equalizer complexity. Moreover, some residual intersymbol interference in the output of the FD-LE can be further removed by an additional nonlinear decision feedback equalizer (DFE) in time domain, because the time domain signal is a digitally modulated symbol. In the conventional DFE, however, the noise is not white at the input of the decision device and correspondingly the decision is not optimum. In this paper, we propose an improved DFE scheme for SC-FDMA systems where a linear noise whitening filter is inserted before the decision device of the conventional DFE scheme. Through computer simulations, we compare the bit error rate performance of the proposed DFE scheme with the conventional equalizers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.58-67
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• 2009

This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within $10{\mu}s$. It is implemented in a $0.18{\mu}m$ CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8 nV/$\sqrt{Hz}$ input referred noise, and 5-dBm $IIP_3$ at 60-mW power consumption. The power detector shows the 35dB dynamic range for 100 MHz input.