• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.855-858
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• 1988

Two methods for probabilistic maintenance scheduling are developed and compared ; one with operation and supplied-shortage cost and other with risk level of LOLP. Based on the real economic power dispatch, quadratic optimal maintenance conditions are obtained and simple amtrix equations are suggested for solutions. Both methods are compared in a sample system of 26,000 [MW] peak and 32,000 [MW] generation capacity.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.13-14
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• 2014

This paper is proposed the PFC control method of boost converter using a charging current of the capacitor. Around AC voltage peak point, PFC operation is stopped and the charging current of the capacitor is flowed. The charging current of the capacitor and the switching current makes the AC input current. The 150[W] converter was confirmed high PF and low THD.

• Proceedings of the Korean Nuclear Society Conference
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• 2005.10a
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• pp.490-491
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• 2005

• International journal of advanced smart convergence
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• v.10 no.4
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• pp.45-51
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• 2021

Polar transmitter can support multi-band and multi-mode operation. The efficiency of frequency usage can be increased if polar transmitters can transmit multi-carrier signals. In this paper the configuration of polar transmitters is investigated to generate multi-carrier signals. Spectrum and CCDF Simulation results of two-carrier signals generated by the polar transmitter can be used to design of PM and AM path in a polar transmitter.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.169-172
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• 2000

This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25 $\mu\textrm{m}$ CMOS technology and consists of about 34.8K gates. Its peak performances is about 250 Mbps under 100 Mhz ECB SEED mode and 125 Mbps under 100 Mhz triple DES mode.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.1
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• pp.44-52
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• 2017

This paper describes a 100 kW high-efficiency isolated DC-DC converter for DC distribution system. The DC-DC converter consists of two dual-active-bridge (DAB) converters in parallel. The operating principle of the DAB converter is explained, and the algorithm for parallel operation of the DAB converters is proposed. Simulation and experiments are conducted to verify the performance of the proposed system. Experimental results demonstrate that the developed converter excellently marks 97.4 percent of peak efficiency under its normal operating condition.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.361-362
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• 2016

Presented in this paper is the design of a high voltage switch module made up of MOSFETs, pulse transformers and their gate driver circuits compactly fitted onto a single PCB module. The ease by which the switch modules can be configured (series stacking and/or parallel stacking) to meet future load variations allows for flexible operation of this design. In addition, the detailed implementation of the gate driver circuit for reliable and easier switch synchronization is also described in this paper. The stored energy in the capacitor bank of a 15kV, 4.5kJ/s peak power capacitor charger was discharged using the developed high voltage switch, and by experimental results, the operation of the proposed circuit was verified to be effectively used as a switch for pulse discharging.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.34 no.5
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• pp.193-200
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• 1985

Increased attention has been given in recent years to the use of pumped hydrostorage plant to meet the requirements for peak generation and bottom pumping. Once a pumped hydrostorage plant is installed, its economic operation as an integral component of a steam generating system requires the selection of a pumping and generating schedule which will result in the most effective use of the hydro generating capacity. The general object of coordination of pumped hydrostorage plants with electric power system is the minimization of the overall procduction cost and the maximization of generation reserves. This paper presents a method for the optimal scheduling of pumped hydrostorage plant and a computer program which determines weekly operating schedules for a pumped hydrostorage plant by dynamic programming method.

• Proceedings of the Korea Multimedia Society Conference
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• 2000.04a
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• pp.117-120
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• 2000

This paper describe VLSL design of crytographic processor which can execute triple DES and DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has 1 unrolled loop structure without pipeline and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation , the key precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O techniques is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is implemented using Altera EPF10K40RC208-4 devices and has peak performance of about 75 Mbps under 20 Mhz ECB DES mode and 25 Mbps uder 20 Mhz triple DES mode.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.9 no.3
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• pp.132-139
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• 1984

This paper presents an exant analysis of the class E tuned power amplifier with a shunt inductor. The following performance parameters are determined for optimum operation with any switch duty ratio: the collector current and voltage waveforms, the peak values of collector current and voltage, the output power, the power output capability, and the values of the load network elements. The analysis shows that the maximum power output capability occurs at a duty ratio of 50 percent. The measured collector efficiency of experiments is 93 percent with 0.93W at 1MHz. This amplifier is especially applicable at portable transmitters because its colletor efficiency is extremely high.