• Korean Journal of Microbiology
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• v.54 no.4
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• pp.325-329
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• 2018

Thp1/PCID2, PCI domain-containing protein, is a component of the evolutionally conserved TREX-2 complex linking mRNA transcription and export. In fission yeast, Schizosaccharomyces pombe, the pci2 (SPBC1105.07c) gene encodes a PCI domain-containing protein that is predicted as a fission yeast orthologue of Thp1 (in budding yeast)/PCID2 (in human). Repression of pci2 expression inhibited both growth and mRNA export. And over-expression of pci2 also exhibited growth retardation with slight accumulation of $poly(A)^+$ RNA in the nucleus. Moreover, yeast two-hybrid and co-immunoprecipitation analysis showed that the Pci2 protein physically interacted with Sac3 and Dss1, which are members of TREX-2 complex. These observations support that the S. pombe Pci2 protein, as a component of TREX-2 complex, is implicated in mRNA export.

• Review of KIISC
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• v.18 no.4
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• pp.66-75
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• 2008

신용카드 및 직불카드 회사들의 연합체인 PCI SSC(PCI Security Standards Council)는 2004년 가정이나 소매상과 같은 소규모 환경에서 고객들의 금융 정보 유출을 방지하기 위한 목적으로 PCI DSS가 제정되었다. 국내에서는 2007년부터 PCI DSS 보안감사제도가 시행되었으며 유일하게 PCI DSS 보안감사자를 보유한 (주)에이쓰리시큐리티사가 가맹점1) 및 PG/VAN사(社)를 대상으로 PCI DSS 보안감사를 실시하였다. 본 연구에서는 2007년 한 해 동안 국내의 PCI DSS 보안감사를 수행하면서 요구사항에 만족하지 못하는 항목들에 대한 사례를 분석함으로써 국내 PCI DSS 보안감사 도입의 현 주소를 파악하고 이에 대한 개선안을 도출하여 보안감사에 보다 유연하게 대처할 수 있도록 하고자 한다. 2007년 한해 국내 보안감사 실시 결과 PCI DSS 보안감사 대상자의 요구사항 준수율은 평균 81%로 측정되었으며, 전체 233개의 요구사항 중 미적용으로 평가된 항목은 평균 38.7개로 나타났다. 전체적인 평균으로 따져봤을 경우 어느 정도 양호한 수준으로 판단할 수도 있으나 피감사 기업의 업태나 사전준비의 유무에 따라 많은 격차가 있었다. 특히, 기반이 튼튼한 PG사나 VAN사에 비해 신규로 등록되어 사업규모가 작거나 타사에 비해 카드결제산업이 차지하는 사업비중이 작은 곳은 PCI DSS 보안감사의 요구사항을 준수하는데 어려움을 겪고 있는 것으로 나타났다. 따라서, 본 연구에서는 PCI DSS 보안감사를 통해 도출된 미적용 사항 중 가장 많은 미적용율을 나타낸 10가지 항목에 대하여 분석하고 이에 대한 대안을 제시함으로써 향후, PCI DSS의 요구사항을 기업환경에 맞게 적용하기 위해 효율적인 가이드로써 활용되었으면 하는 바램이다.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.74-85
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• 2015

PCI Express is a well-known and widely used de-facto system bus standard for connecting among a processor and IO devices. PCI Express is originated from old PCI standard, and its most of applications are limited to be used within a PC or server system. But, because of its fast speed, low power consumption, and good protocol efficiency, it is considered as one of a good candidate for an alternate system interconnect for many years. In this paper, we present design, implementation and early evaluation of an alternate system interconnect by utilizing PCI Express. The developed alternate system interconnect using PCI Express (named PCIeLINK) utilizes non-transparent bridging (NTB) technic which generally used in fail-over system in PCI and PCI Express. By using NTB technic, PCI Express device can be extended to outside of a system without electrical and logical problems arising during system boot and enumeration. To build up an alternate system interconnect, we designed and implemented a network interface card having multiple PCI Express ${\times}4$ connections (theoretically 20 Gbps) and tested, The early test results revealed that an ${\times}4$ port in the card showed 8.6 Gbps peak performance for bulk transmission and 5.1 Gbps peak for normal TCP/IP transfer.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.499-502
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• 1999

This paper presents a PCI (Peripheral Component Interconnect) controller embedded in a multimedia processor, called FLOVA (FLOating point VLIW Architecture), targeting for 3D graphics applications. Fast I/O interfaces are essential for multimedia processors which usually handle large amount of multimedia data. Therefore, in FLOVA, PCI bus is adopted for I/O interface due to fast burst transaction. However, there are several problems in implementation and verification to use burst transaction of PCI. It is difficult to handle data transaction between two units which have two different operating frequency. FLOVA has more higher operating frequency about 100MHz than that of PCI local bus and it makes lower utilization of FLOVA bus. Also, traditional simulation is not sufficient for verification of PCI functionality. In this paper, we propose buffering schemes to implement the PCI controller with wide bandwidth and high bus utilization. Also, this paper shows how to verify the PCI controller using real PCI bus environments before its fabrication.

• The KIPS Transactions:PartA
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• v.12A no.6 s.96
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• pp.523-530
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• 2005

When a PCI 2.2 bus master requests data using Memory Read command, a target device may hold PCI bus without data to be transferred for long time because a target device needs time to prepare data infernally. Because the usage efficiency of the PCI bus and the data transfer efficiency are decreased due to this situation, the PCI specification recommends to use the Delayed Transaction mechanism to improve the system performance. But the mechanism cann't fully improve performance because a target device doesn't know the exact size of prefetched data. In the previous work, we propose a new method called Prefetch Request when a bus master intends to read data from the target device. In this paper, we design PCI 2.2 controller and local device that support the proposed method. The designed PCI 2.2 controller has simple local interface and it is used to convert the PCI protocol into the local protocol. So the typical users, who don't know the PCI protocol, can easily design the PCI target device using the proposed PCI controller. We propose the basic behavioral verification, hardware design verification, and random test verification to verify the designed hardware. We also build the test bench and define assembler instructions. And we propose random testing environment, which consist of reference model, random generator ,and compare engine, to efficiently verify corner case. This verification environment is excellent to find error which is not detected by general test vector. Also, the simulation under the proposed test environment shows that the proposed method has the higher data transfer efficiency than the Delayed Transaction about $9\%$.

• Journal of IKEEE
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• v.23 no.3
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• pp.941-946
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• 2019

In this paper, the author analyzed the PCI (Physical Cell Identification) allocation methods in the LTE (Long Term Evolution) SON (Self Organization Network) environment. A variety of techniques have been proposed for how to allocate PCI, and the LTE standard fundamentally explained that collision between a cell and neighbor cells arise while a cell assign the PCI. Therefore, in this paper, the author examined the scenarios of PCI collision, weak collision, and confusion proposed by LTE specification. In addition, the cell central approach and the distributed approach were discussed as solutions for each scenario. In this paper, the author reviewed the approach of graphic coloring technique which was studied recently and explained the strategy of central approach.

• Journal of Korean Society for Quality Management
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• v.31 no.1
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• pp.109-122
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• 2003

This paper presents a robust process capability index(PCI) based on the expected loss derived from the empirical distribution function(EDF). We propose the EDF expected loss in order to develop a PCI that does not depends on the underlying process distribution. The EDF expected loss depends only on the sample data, so the PCI based on it is robust and it does nor require complex calculations. The inverted normal loss function(INLF) is employed in order to overcome the drawback of the quadratic loss which may Increase unboundedly outside the specification limits. A comprehensive simulation study was performed under various process distributions, in order to compare the accuracy and the precision of the proposed PCI with those of the PCI based on the expected loss derived from the normal distribution. The proposed PCI turned out to be more accurate than the normal PCI in most cases, especially when the process distribution has high kurtosis or skewness. It is expected that the proposed PCI can be utilized In real processes where the true distribution family may not be known.

• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.1
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• pp.9-16
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• 2007

본 논문에서는 차세대 통신 플랫폼을 위한 PCI 익스프레스의 전송계층과 데이터 연결계층의 모든 기능을 지원하는 PCI 익스프레스 컨트롤러를 설계하였다. 설계된 컨트롤러를 효과적으로 제어하기 위해 8051 마이크로프로세서를 이용하였다. 또한, 본 논문에서는 PCI 익스프레스 컨트롤러와 8051 마이크로프로세서의 통합 검증을 위한 방법으로 벡터 생성 부분, 테스트 벤치, 그리고 메모리로 구성된 테스트 벤치를 하나의 가상 마이크로프로세서로 가정하였다. 그리고 PCI 익스프레스의 모든 프로토콜을 지원할 수 있는 어셈블리 수준의 명령어들을 테스트 벤치에 적용되도록 하였다. 특히 일반적인 기본 동작 검증과 설계 기반 검증에서 찾지 못한 특수 경우의 에러를 찾기 위한 검증을 위해 랜덤 검증 환경 및 테스트 파라미터를 정의 하였다. 제안된 검증 환경과 명령어를 통해 설계된 PCI 컨트롤러의 검증 결과 랜덤 테스트 검증을 통해 효과적으로 오류를 찾을 수 있었다.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.811-814
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• 2003

Today's and tomorrow's processors and I/O devices are demanding much higher I/O bandwidth than PCI 2.3 or PCI-X can deliver and it is time to engineer a new generation of PCI to serve as a standard I/O bus for future generation platforms. According to this demand the PCI SIG proposed PCI Express. This paper describes about the design of PCI Express Behavioral Model. A Behavioral Model enables the designers to test whether the design specifications are met by performing computer simulations rather than experiments on the physical prototype. In the proposed Model, we can verify whether our design concept satisfies the PCI Express functional protocol.

• Journal of the Korean Institute of Intelligent Systems
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• v.11 no.8
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• pp.764-770
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• 2001

In this paper, we propose a novel PCI bus based parallel fuzzy inference system for transferring and inferencing the large volumes of fuzzy data in high speed. For this, the PCI 9050 interface chip is used to connect a local bus design as a PCI target core using FPGA to the PCI bus. We design and implement the PCI target core by using VHDL to be processed in parallel by considering the points of parallelyzing each element of the membership functions and each block of the condition and/or consequent parts. The proposed system can be used in a system requiring a rapid inference time in a real-time system or pattern recognition on the large volume of satellite images that have many inference variables in the condition and consequent parts.