• 한국정밀공학회지
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• 제21권12호
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• pp.160-166
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• 2004

Self-Assembled Monolayers(SAMs) by alkanethiol adsorption to thin metal film are widely being investigated fer applications as coating layer for anti-stiction or friction reduction and in fabrication of micro structure of molecule and bio molecule. Recently, there have been many researches on micro patterning using the advantages of very thin thickness and etching resistance of Self-Assembled Monolayers in selective etching of thin metal film. In this report, we present the several machining method to form the nanoscale structure by Mask-Less laser patterning using alknanethiolate Self-Assembled Monolayers such as thin metal film etching and heterogeneous SAMs structure formation.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2003년도 춘계학술대회 논문집
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• pp.219-222
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• 2003

Self-Assembled Monolayers(SAMs) by alkanethiol adsorption to thin metal film are widely being investigated for applications as coating layer for anti-stiction or friction reduction and in fabrication of micro structure of molecular and bio molecular. Recently, there have been many researches on micro patterning using the advantages of very thin thickness and etching resistance in selective etching of thin metal film of Self- Assembled Monolayers. In this report, we present the micromachining thin metal film by Mask-Less laser patterning of alknanethiolate Self-Assembled Monolayers.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 추계학술대회 논문집
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• pp.330-333
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• 2005

The fabrication of mold fur nano imprint lithography (NIL) is experimentally reported using the scanning probe lithography (SPL) technique, instead of the conventional I-beam lithography technique. The nanometer scale patterning structure is fabricated by the localized generation of oxide patterning on the silicon (100) wafer surface with a thin oxide layer, The fabrication method is based on the contact mode of scanning probe microscope (SPM) in air, The precision cleaning process is also performed to reach the low roughness value of $R_{rms}=0.084 nm$, which is important to increase the reproducibility of patterning. The height and width of the oxide dot are generated to be 15.667 nm and 209.5 nm, respectively, by applying 17 V during 350 ms.

• Journal of Information Display
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• 제10권3호
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• pp.111-116
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• 2009

In this paper, a plasma-assisted patterning method for the organic layers of organic light-emitting diodes (OLEDs) and its effect on the OLED performances are reported. Oxygen plasma was used to etch the organic layers, using the top electrode consisting of lithium fluoride and aluminum as an etching mask. Although the current flow at low voltages increased for the etched OLEDs, there was no significant degradation of the OLED efficiency and lifetime in comparison with the conventional OLEDs. Therefore, this method can be used to reduce the ohmic voltage drop along the common top electrodes by connecting the top electrode with highly conductive bus lines after the common organic layers on the bus lines are etched by plasma. To further analyze the current increase at low voltages, the plasma patterning effect on the OLED performance was investigated by changing the device sizes, especially in one direction, and by changing the etching depth in the vertical direction of the device. It was found that the current flow increase at low voltages was not proportional to the device sizes, indicating that the current flow increase does not come from the leakage current along the etched sides. In the etching depth experiment, the current flow at low voltages did not increase when the etching process was stopped in the middle of the hole transport layer. This means that the current flow increase at low voltages is closely related to the modification of the hole injection layer, and thus, to the modification of the interface between the hole injection layer and the bottom electrode.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.9-10
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• 2006

The patterning for the active layer of organic semiconductors is important to attain completely organic-based OTFTs(Organic Thin Film Transistors). We studied on possibility of the application of the conventional photolithography technique to pattern the organic active layer poly(3-hexylthiophene)(P3HT). Patterned P3HT-based OTFTs with Bottom Contact(BC) configuration were fabricated using the conventional photolithography. We achieved field-effect mobilities in the saturation regime ${\sim}1.2{\times}10^{-3}cm^2/V{\cdot}s$, $I_{on/off}$ ratios ${\sim}10^5$ in the subtractive method, ${\sim}8{\times}10^{-4}cm^2/V{\cdot}s$, $I_{on/off}$ ratios ${\sim}10^3$ in the additive one.

• Journal of Information Display
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• 제9권1호
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• pp.14-19
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• 2008

We demonstrated the capillary force lithography (CFL) method for controlling the azimuthal anchoring energy of a liquid crystal (LC) alignment layer. When a thermoplastic polymer film is heated to over the glass transition temperature, the melted polymer is filled into the mold structure by the capillary action and the aspect ratio of the pattern is determined by the dewetting time of the CFL process. Here, the proposed method showed that the azimuthal anchoring energy of the LC alignment layer could be simply controlled by the surface relief patterns which were determined by the dewetting times during the CFL patterning.

• Transactions on Electrical and Electronic Materials
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• 제11권4호
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• pp.190-193
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• 2010

This report covers an effective fabrication method of graphene nanoribbon for top-gated field effect transistors (FETs) utilizing electron beam lithography with a bi-layer resists (XR-1541/poly methtyl methacrylate) process. To improve the variation of the gating properties of FETs, the residues of an e beam resist on the graphene channel are successfully taken off through the combination of reactive ion etching and a lift-off process for the XR-1541 bi-layer. In order to identify the presence of graphene structures, atomic force microscopy measurement and Raman spectrum analysis are performed. We believe that the lift-off process with bi-layer resists could be a good solution to increase gate dielectric properties toward the high quality of graphene FETs.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.1494-1495
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• 2009

Thin Film Transistor(TFT) having CIS (CuInSe) semiconductor layer was fabricated and characterized. Heavily doped Si was used as a common gate electrode and PECVD Silicon nitride ($SiN_x$) was used as a gate dielectric material for the TFT. Source and drain electrodes were deposited on the $SiN_x$ layer and CIS layer was formed by a direct patterning method between source and drain electrodes. Nanoparticle of CIS material was used as the ink of the direct patterning method.

• 한국기계가공학회지
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• 제18권2호
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• pp.38-43
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• 2019

Electrochemical etching is a popular process to apply metal patterning in various industries. In this study, the electrochemical etching using a patterned copper layer was proposed to fabricate multilayered structures. The process consists of electrodeposition, laser patterning, and electrochemical etching, and a repetition of this process enables the production of multilayered structures. In the fabrication of a multilayered structure, an etch factor that reflects the etched depth and pattern size should be considered. Hence, the etch factor in the electrochemical etching process using the copper layer was calculated. After the repetition process of electrochemical etching using copper layers, the surface characteristics of the workpiece were analyzed by EDS analysis and surface profilometer. As a result, multilayered structures with various shapes were successfully fabricated via electrochemical etching using copper layers.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.436-437
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• 2012

Double patterning technology (DPT) has been suggested as a promising candidates of the next generation lithography technology in FLASH and DRAM manufacturing in sub-40nm technology node. DPT enables to overcome the physical limitation of optical lithography, and it is expected to be continued as long as e-beam lithography takes place in manufacturing. Several different processes for DPT are currently available in practice, and they are litho-litho-etch (LLE), litho-etch-litho-etch (LELE), litho-freeze-litho-etch (LFLE), and self-aligned double patterning (SADP) [1]. The self-aligned approach is regarded as more suitable for mass production, but it requires precise control of sidewall space etch profile for the exact definition of hard mask layer. In this paper, we propose etch end point detection (EPD) in spacer etching to precisely control sidewall profile in SADP. Conventional etch EPD notify the end point after or on-set of a layer being etched is removed, but the EPD in spacer etch should land-off exactly after surface removal while the spacer is still remained. Precise control of real-time in-situ EPD may help to control the size of spacer to realize desired pattern geometry. To demonstrate the capability of spacer-etch EPD, we fabricated metal line structure on silicon dioxide layer and spacer deposition layer with silicon nitride. While blanket etch of the spacer layer takes place in inductively coupled plasma-reactive ion etching (ICP-RIE), in-situ monitoring of plasma chemistry is performed using optical emission spectroscopy (OES), and the acquired data is stored in a local computer. Through offline analysis of the acquired OES data with respect to etch gas and by-product chemistry, a representative EPD time traces signal is derived. We found that the SE-EPD is useful for precise control of spacer etching in DPT, and we are continuously developing real-time SE-EPD methodology employing cumulative sum (CUSUM) control chart [2].