• Elastomers and Composites
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• v.34 no.1
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• pp.45-52
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• 1999

This paper describes how the gold particles self assemble on the specific phase on the microphase separated block copolymer thin film and form a well ordered patterns. For this study, polystyrene-polybutadiene-polystyrene (PS-PB-PS) triblock copolymer (30wt % PS) thin films (${\sim}100nm$) having a cylindrical morphology were cast from 0.1wt% toluene solution to be used as polymer thin film templates. The films having either vertical PS cylinders or in-plane PS cylinders in PB matrix from each different solvent evaporation condition were obtained. Cross-sectional transmission electron microscopy(TEM) was used to study the surface and bulk morphologies of block copolymer thin films. Small amount of gold particles was evaporated on a block copolymer thin film template to obtain a nano-scale pattern. When an as-cast thin film template was used, gold particles preferentially self assemble on the low surface tension PB phase and a relatively well ordered pattern in nano-scale was produced. However, after the formation of a low surface energy PB rich layer upon annealing, a gold self-assembled pattern was not observed.

• KSBB Journal
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• v.22 no.6
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• pp.433-437
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• 2007

A constant desire has been to fabricate nanopatterns for biochip and the Ultraviolet-nano imprint lithography (UV-NIL) is promising technology especially compared with thermal type in view of cost effectiveness. By using this method, nano-scale to micro-scale structures also called nanopore structures can be fabricated on large scale gold plate at normal conditions such as room temperature or low pressure which is not possible in thermal type lithography. One of the most important methods in fabricating biochips, immobilizing, was processed successfully by using this technology. That means immobilizing proteins only on the nanopore structures based on gold, not on hardened resin by UV is now possible by utilizing this method. So this selective nano-patterning process of protein can be useful method fabricating nanoscale protein chip.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.33-33
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• 2007

SoP-L 공정은 유전율이 상이한 재료를 이용하여 PCB 공정이 가능하고 다른 packaging 방법에 비해 공정 시간과 비용이 절약되는 잠정이 있다. 본 연구에서는 SoP-L 기술을 이용하여 Si 기판의 함몰에 판한 공정의 안정도와 함몰 시 제작된 때턴의 특성의 변화에 대해 관찰 하였다. Si 기판의 함몰에 Active device를 이용하여 특성의 변화를 살펴보고 공정의 안정도를 확립하려 했지만 Active device는 측정 시 bias의 확보와 특성의 민감한 변화로 인해 비교적 측정이 용이하고 공정의 test 지표를 삼기 위해 passive device 를 구현하여 함몰해 보았다. Passive device 의 제작 과정은 Si 기판 위에 spin coating을 통해 PI(Poly Imide)를 10um로 적층한 후에 Cr과 Au를 seed layer로 증착을 하였다. 그리고 photo lithography 공정을 통하여 photo resister patterning 후에 전해 Cu 도금을 거쳐 CPW 구조로 $50{\Omega}$ line 과 inductor를 형성하였다. 제작 된 passive device의 함몰 전 특성 추출 data와 SoP-L공정을 통한 함몰 후 추출 data 비교를 통해 특성의 변화와 공정의 안정도를 확립하였다. 차후 안정된 SoP-L 공정을 이용하여 Active device를 함몰 한다면 특성의 변화 없이 size 룰 줄이는 효과와 외부 자극에 신뢰도가 강한 기판이 제작 될 것으로 예상된다.

• Polymer(Korea)
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• v.28 no.4
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• pp.305-313
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• 2004

A vacuum pressure-difference technique for making a nano-precision replica is investigated for various applications. Master patterns for replication were fabricated using a nano-replication printing (nRP) process. In the nRP process, any picture and pattern can be replicated from a bitmap figure file in the range of several micrometers with resolution of 200nm. A liquid-state monomer is solidified by two-photon absorption (TPA) induced by a femto-second laser according to a voxel matrix scanning. After polymerization, the remaining monomers were removed simply by using ethanol droplets. And then, a gold metal layer of about 30nm thickness was deposited on the fabricated master patterns prior to polydimethylsiloxane molding for preventing bonding between the master and the polydimethylsiloxane mold. A few gold particles attached on the polydimethylsiloxane stamp during detaching process were removed by a gold selecting etchant. After fabricating the polydimethylsiloxane mold, a nano-precision polydimethylsiloxane replica was reproduced. More precise replica was produced by the vacuum pressure-difference technique that is proposed in this paper. Through this study, direct patterning on a glass plate, replicating a polydimethylsiloxane mold, and reproducing polydimethylsiloxane replica are demonstrated with a vacuum pressure-difference technique for various micro/nano-applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.2
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• pp.13-21
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• 2000

Au-black for the application of the long wavelength infrared absorber has been prepared by evaporating Au under nitrogen gas-filled low vacuum condition. Characteristics of the deposited Au-black were carefully investigated through structural analysis, infrared absorbance measurement, and patterning of the layer, all of which are dependent on the deposition condition. High density of micro-cavity that trapped infrared were obtained, and infrared absorbance in the wavelength range from 3 $\mu\textrm{g}$ to 14 $\mu\textrm{g}$ was found to be about 90% when the Au-black layer was produced under the deposition condition of mass Per area of about 600 $\mu\textrm{g}$/cm$^{2}$ and chamber pressure of above 1 Torr. Photoresist lift-off process could be performed to pattern the Au-black, of which mass per area was below 900 $\mu\textrm{g}$/cm/ sup 2/. In view of absorbance, heat capacity, and pattern formation, the deposition condition of chamber pressure of about 1 Tow and mass per area of about 600$\mu\textrm{g}$/cm$^{2}$ was most adequate for preparing the Au-black as an infrared absorber.

• Proceedings of the Korean Magnestics Society Conference
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• 2010.06a
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• pp.79-79
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• 2010

Semimetallic bismuth (Bi) has been extensively investigated over the last decade since it exhibits very intriguing transport properties due to their highly anisotropic Fermi surface, low carrier concentration, long carrier mean free path l, and small effective carrier mass $m^*$. In particular, the great interest in Bi nanowires lies in the development of nanowire fabrication methods and the opportunity for exploring novel low-dimensional phenomena as well as practical application such as thermoelectricity[1]. In this work, we introduce a self-assembled interconnection of nanostructures produced by an on-film formation of nanowires (OFF-ON) method in order to form a highly ohmic Bi nanobridge. A Bi thin film was first deposited on a thermally oxidized Si (100) substrate at a rate of $40\;{\AA}/s$ by radio frequency (RF) sputtering at 300 K. The sputter system was kept in an ultra high vacuum (UHV) of $10^{-6}$ Torr before deposition, and sputtering was performed under an Ar gas pressure of 2m Torr for 180s. For the lateral growth of Bi nanowires, we sputtered a thin Cr (or $SiO_2$) layer on top of the Bi film. The Bi thin films were subsequently put into a custom-made vacuum furnace for thermal annealing to grow Bi nanowires by the OFF-ON method. After thermal annealing, the Bi nanowires cannot be pushed out from the topside of the Bi films due to the Cr (or $SiO_2$) layer. Instead, Bi nanowires grow laterally as a mean s of releasing the compressive stress. We fabricated a self-assembled Bi nanobridge (d=192 nm) device in-situ using OFF-ON through annealing at $250^{\circ}C$ for 10hours. From I-V measurements taken on the Bi nanobridge device, contacts to the nanobridge were found highly ohmic. The quality of the Bi nanobridge was also proved by the high MR of 123% obtained from transverse MR measurements. These results manifest the possibility of self-assembled nanowire interconnection between various nanostructures for a variety of applications and provide a simple device fabrication method to investigate transport properties on nanowires without complex patterning and etching processes.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.53-58
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• 2018

Since the scaling-down of IC devices has been reached to their physical limitations, several innovative packaging technologies such as 3D packaging, embedded packaging, and fan-out wafer level packaging (FOWLP) are actively studied. In this study the fabrication of organic-inorganic dielectric material was evaluated for the use of multi-structured redistribution layers (RDL) in FOWLP. Compared to current organic dielectrics such as PI or PBO an organic-inorganic hybrid dielectric called polysilsesquioxane (PSSQ) can improve mechanical, thermal, and electrical stabilities. polysilsesquioxane has also an excellent advantage of simultaneous curing and patterning through UV exposure. The polysilsesquioxane samples were fabricated by spin-coating on 6-inch Si wafer followed by pre-baking and UV exposure. With the 10 minutes of UV exposure polysilsesquioxane was fully cured and showed $2{\mu}m$ line-pattern formation. And the dielectric constant of cured polysilsesquioxane dielectrics was ranged from 2.0 to 2.4. It has been demonstrated that polysilsesquioxane dielectric can be patterned and cured by UV exposure alone without a high temperature curing process.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.330-332
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• 2013

소 분위기에서 플라즈마 표면 처리의 경우 기판 표면에 존재하는 수소와 탄소 유기물들이 산소와 반응하여 $H_2O$와 $CO_2$ 등으로 제거되며 표면에 오존 결합을 유도하여 표면 에너지를 증가시키는 것으로 알려져 있다. ZnO 나노구조물을 성장시키는 방법으로는 MOCVD (Metal-Organic Chemical Vapor Deposited), PLD (Pulsed Laser Deposition), VLS (Vapor-Liquid-Solid), Sputtering, 습식화학합성법(Wet Chemical Method) 방법 등이 있다. 그중에서도 습식화학합성법은 쉽게 구성요소를 제어할 수 있고, 저비용 공정과 낮은 온도에서 성장 가능하며 플렉서블 소자에도 적용이 가능하다. 그러므로 본 연구에서는 플라즈마 표면처리에 따라 표면에너지를 변화하여 습식화학합성법으로 성장시킨 ZnO nanorods의 밀도를 제어하고 photolithography 공정 없이 패터닝 가능성을 유 무를 판단하는 연구를 진행하였다. 기판은 Si wafer (100)를 사용하였으며 세척 후 표면에너지 증가를 위한 플라즈마 표면처리를 실시하였다. 분위기 가스는 Ar/$O_2$를 사용하였으며 입력전압 400 W에서 0, 5, 10, 15, 60초 동안 각각 실시하였다. ZnO nanorods의 seed layer를 도포하기 위하여 Zinc acetate dehydrate [Zn $(CH_3COO)_2{\cdot}2H_2O$, 0.03 M]를 ethanol 50 ml에 용해시킨 후 스핀코팅기를 이용하여 850 RPM, 15초로 5회 실시하였으며 $80^{\circ}C$에서 5분간 건조하였다. ZnO rods의 성장은 Zinc nitrate hexahydrate [$Zn(NO_3)_2{\cdot}6H_2O$, 0.025M], HMT [$C6H_{12}N_4$, 0.025M]를 deionized water 250 ml에 용해시켜 hotplate에 올리고 $300^{\circ}C$에서 녹인 후 $200^{\circ}C$에서 3시간 성장시켰다. ZnO nanorods의 성장 공정은(Fig. 1)과 같다. 먼저 플라즈마 처리한 시편의 표면에너지 측정을 위해 접촉각 측정 장치[KRUSS, DSA100]를 이용하였다. 그 결과 0, 5, 10, 15, 60 초로 플라즈마 표면 처리했던 시편이 각각 Fig. l, 2와 같이 $79^{\circ}$, $43^{\circ}$, $11^{\circ}$, $6^{\circ}$, $7.8^{\circ}$로 측정되었으며 이것을 각각 습식화학합성법으로 ZnO nanorods를 성장 시켰을 때 Fig. 3과 같이 밀도 차이를 확인할 수 있었다. 이러한 결과를 바탕으로 기판의 표면에너지를 제어하여 Fig. 4와 같이 나타나며 photolithography 공정없이 ZnO nanorods를 패터닝을 할 수 있었다. 본 연구에서는 플라즈마 표면 처리를 통하여 표면에너지의 변화를 제어함으로써 ZnO nanorods 성장의 밀도 차이를 나타냈었다. 이러한 저비용, 저온 공정으로 $O_2$, CO, $H_2$, $H_2O$와 같은 다양한 화학종에 반응하는 ZnO를 이용한 플렉시블 화학센서에 응용 및 사용될 수 있고, 플렉시블 디스플레이 및 3D 디스플레이 소자에 활용 가능하다.

• Corrosion Science and Technology
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• v.9 no.6
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• pp.276-280
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• 2010

Copper(Cu) as an interconnecting metal layer can replace aluminum (Al) in IC fabrication since Cu has low electrical resistivity, showing high immunity to electromigration compared to Al. However, it is very difficult for copper to be patterned by the dry etching processes. The chemical mechanical polishing (CMP) process has been introduced and widely used as the mainstream patterning technique for Cu in the fabrication of deep submicron integrated circuits in light of its capability to reduce surface roughness. But this process leaves a large amount of residues on the wafer surface, which must be removed by the post-CMP cleaning processes. Copper corrosion is one of the critical issues for the copper metallization process. Thus, in order to understand the copper corrosion problems in post-CMP cleaning solutions and study the effects of DC biases and post-CMP cleaning solution concentrations on the Cu film, a constant voltage was supplied at various concentrations, and then the output currents were measured and recorded with time. Most of the cases, the current was steadily decreased (i.e. resistance was increased by the oxidation). In the lowest concentration case only, the current was steadily increased with the scarce fluctuations. The higher the constant supplied DC voltage values, the higher the initial output current and the saturated current values. However the time to be taken for it to be saturated was almost the same for all the DC supplied voltage values. It was indicated that the oxide formation was not dependent on the supplied voltage values and 1 V was more than enough to form the oxide. With applied voltages lower than 3 V combined with any concentration, the perforation through the oxide film rarely took place due to the insufficient driving force (voltage) and the copper oxidation ceased. However, with the voltage higher than 3 V, the copper ions were started to diffuse out through the oxide film and thus made pores to be formed on the oxide surface, causing the current to increase and a part of the exposed copper film inside the pores gets back to be oxidized and the rest of it was remained without any further oxidation, causing the current back to decrease a little bit. With increasing the applied DC bias value, the shorter time to be taken for copper ions to be diffused out through the copper oxide film. From the discussions above, it could be concluded that the oxide film was formed and grown by the copper ion diffusion first and then the reaction with any oxidant in the post-CMP cleaning solution.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.4
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• pp.366-372
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• 2019

In this paper, we fabricated a capacitive humidity sensor with an IDT(Interdigitated) electrode using commercial polyimide containing fluorine, and its properties were measured and analyzed. First, in order to analyze the composition of commercial polyimide, EDS analysis was performed after patterning process on a silicon wafer. The area of the humidity sensor was $1.56{\times}1.66mm^2$, and the width of the electrode and the gap between the electrodes were $3{\mu}m$ each. The number of electrodes was 166 and the length of the electrode was 1.294mm for the sensitivity of the sensor. The fabricated sensor showed that the sensitivity was 24 fF/%RH, linearity <${\pm}2.5%RH$ and hysteresis <${\pm}4%RH$. As a result of measuring the capacitance value according to the frequency change, the capacitance vlaue decreased with increasing frequency. Capacitance deviations with 10kHz and 100kHz were measured as 0.3pF on average.