• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.252.2-252.2
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• 2013

ZnO nanostructures have a lot of interest for decades due to its varied applications such as light-emitting devices, power generators, solar cells, and sensing devices etc. To get the high performance of these devices, the factors of nanostructure geometry, spacing, and alignment are important. So, Patterning of vertically- aligned ZnO nanowires are currently attractive. However, many of ZnO nanowire or nanorod fabrication methods are needs high temperature, such vapor phase transport process, metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy, thermal evaporation, pulse laser deposition and thermal chemical vapor deposition. While hydrothermal process has great advantages-low temperature (less than $100^{\circ}C$), simple steps, short time consuming, without catalyst, and relatively ease to control than as mentioned various methods. In this work, we investigate the dependence of ZnO nanowire alignment and morphology on si substrate using of nanosphere template with various precursor concentration and components via hydrothermal process. The brief experimental scheme is as follow. First synthesized ZnO seed solution was spun coated on to cleaned Si substrate, and then annealed $350^{\circ}C$ for 1h in the furnace. Second, 200nm sized close-packed nanospheres were formed on the seed layer-coated substrate by using of gas-liquid-solid interfacial self-assembly method and drying in vaccum desicator for about a day to enhance the adhesion between seed layer and nanospheres. After that, zinc oxide nanowires were synthesized using a low temperature hydrothermal method based on alkali solution. The specimens were immersed upside down in the autoclave bath to prevent some precipitates which formed and covered on the surface. The hydrothermal conditions such as growth temperature, growth time, solution concentration, and additives are variously performed to optimize the morphologies of nanowire. To characterize the crystal structure of seed layer and nanowires, morphology, and optical properties, X-ray diffraction (XRD), field emission scanning electron microscopy (FE-SEM), Raman spectroscopy, and photoluminescence (PL) studies were investigated.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.506-508
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• 2005

In general, organic TFTs are comprised of four components: gate electrode, gate dielectric, organic active semiconductor layer, and source and drain contacts. The TFT current, in turn, is typically determined by channel length and width, carrier field effect mobility, gate dielectric thickness and permittivity, contact resistance, and biasing conditions. More recently, a number of techniques and processes have been introduced to the fabrication of OTFT circuits and displays that aim specifically at reduced fabrication cost. These include microcontact printing for the patterning of metals and dielectrics, the use of photochemically patterned insulating and conducting films, and inkjet printing for the selective deposition of contacts and interconnect pattern. In the fabrication of organic TFTs, microcontact printing has been used to pattern gate electrodes, gate dielectrics, and source and drain contacts with sufficient yield to allow the fabrication of transistors. We were fabricated a pentacene OTFTs on flexible PEN film. Au/Cr was used for the gate electrode, parylene-c was deposited as the gate dielectric, and Au/Cr was chosen for the source and drain contacts; were all deposited by ion-beam sputtering and patterned by microcontact printing and lift-off process. Prior to the deposition of the organic active layer, the gate dielectric surface was treated with octadecyltrichlorosilane(OTS) from the vapor phase. To complete the device, pentacene was deposited by thermal evaporation and patterned using a parylene-c layer. The device was shown that the carrier field effect mobility, the threshold voltage, the subthreshold slope, and the on/off current ratio were improved.

• Journal of the Korean Magnetics Society
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• v.19 no.2
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• pp.52-56
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• 2009

Interlayer coupling field, coercivity, magnetoresitance ratio, and magnetic sensitivity depending on the thickness of free CoFe layer for the CoFe/Cu/CoFe/IrMn multilayer are investigated. In case of CoFe layer of $30\;{\AA}$ thickness for the CoFe(t)/Cu($25\;{\AA}$)/CoFe($60\;{\AA}$)/IrMn($80\;{\AA}$) multilayer with ferromagnet/non-magnet/ferromagnet structure induced by IrMn layer, the lowest coercivity and the highest magnetic sensitivity, which is contained soft magnetic property, are observed. On the other side, in case of CoFe layer of $90\;{\AA}$ thickness, there are the highest coercivity and the lowest magnetic sensitivity. The fabricated CoFe($30\;{\AA}$)/Cu($25\;{\AA}$)/CoFe($60\;{\AA}$)]/IrMn($80\;{\AA}$) spin valve device with $2{\times}8{\mu}m^2$ patterning size are measured by two probe method, which is selected the sensing current as the longitudinal direction and the easy axis as the transversal direction. The measuring magntoresistance ratio and magnetic sensitivity of GMR-SV device having the soft magnetic property are 3.0% and 0.3%/Oe, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1393-1398
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• 2009

Conventionally, etching is first considered for microelectronics fabrication process and is specially important in process of a-Si:H thin film transistor for LCD. In this paper, we stabilize properties of device by development of wet and dry etching process. The a-Si:H TFTs of this paper is inverted staggered type. The gate electrode is lower part. The gate electrode is formed by patterning with length of 8 ${\mu}$m${\sim}$16 ${\mu}$m and width of 80${\sim}$200 ${\mu}$m after depositing with gate electrode (Cr) 1500 ${\AA}$under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photo resistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN:H (2000 ${\mu}$m), a-Si:H(2000 ${\mu}$m) and n+a-Si:H (500 ${\mu}$m), We have deposited n-a-Si:H, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. In the fabricated TFT, the most frequent problems are over and under etching in etching process. We were able to improve properties of device by strict criterion on wet, dry etching and cleaning process.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.7
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• pp.33-39
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• 2015

In this work, SU-8 passivated IZO thin-film transistors(TFTs) made by solution-processes was investigated for enhancing stability of indium zinc oxide(IZO) TFT. A very viscous negative photoresist SU-8, which has high mechanical and chemical stability, was deposited by spin coating and patterned on top of TFT by photo lithography. To investigate the enhanced electrical performances by using SU-8 passivation layer, the TFT devices were analyzed by X-ray phtoelectron spectroscopy(XPS) and Fourier transform infrared spectroscopy(FTIR). The TFTs with SU-8 passivation layer show good electrical characterestics, such as ${\mu}_{FE}=6.43cm^2/V{\cdot}s$, $V_{th}=7.1V$, $I_{on/off}=10^6$, SS=0.88V/dec, and especially 3.6V of ${\Delta}V_{th}$ under positive bias stress (PBS) for 3600s. On the other hand, without SU-8 passivation, ${\Delta}V_{th}$ was 7.7V. XPS and FTIR analyses results showed that SU-8 passivation layer prevents the oxygen desorption/adsorption processes significantly, and this feature makes the effectiveness of SU-8 passivation layer for PBS.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.6
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• pp.1099-1103
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• 2007

TFT's have been intensively researched for possible electronic and display applications. Through tremendous engineering and scientific efforts, a-Si:H TFT fabrication process was greatly improved. In this paper, the reason on defects occurring at a-Si:H TFT fabrication process is analyzed and solved, so a-Si:H TFT's yield is increased and reliability is improved. The a-Si:H TFT of this paper is inverted staggered type TFT. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr). We have fabricated a-SiN:H, conductor, etch-stopper and photo-resistor on gate electrode in sequence, respectively. We have deposited n+a-Si:H, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-slower pattern. The NPR layer by inverting pattern of upper Sate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFT made like this has problems at photo-lithography process caused by remains of PR. When sample is cleaned, this remains of PR makes thin chemical film on surface and damages device. Therefor, in order to improve this problem we added ashing process and cleaning process was enforced strictly. We can estimate that this method stabilizes fabrication process and makes to increase a-Si:H TFT's yield.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.11a
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• pp.226-227
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• 2014

We demonstrate nanoscale local anodic oxidation (LAO) patterning on few layer graphene using atomic force microscope (AFM) at room temperature and normal atmosphere. We focus on the humidity dependency in nanoscale oxidation of graphene. The relationship between the oxidation size and the AFM setting values, such as set point, tip speed, and humidity are observed. By changing these values, proper parameters were found to produce features on demand size. This technique provides an easy way to form graphene oxide lithography without any chemical resists. We have obtained oxidation size down to 50-nm with 6-nm-height oxide barrier line with $0.1{\mu}m/s$ tip scanning speed and micrometer size symbols on a graphene flake. We attribute the bumps to local anodic oxidation on graphene surface and combination of oxygen ions into the graphene lattice.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.214-217
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• 1999

We investigated the quench characteristics of meander line type resistive superconducting fault current limiters based on YBCO thin films grown on 2" diameter LaAlO$_3$ substrates. A gold layer was deposited onto the 0.4 ${\mu}$ m thick YBCO film to disperse the heat generated at hot spots, prior to patterning into 1 mm wide meander lines by photolithography. The limiters were tested with simulated fault currents of various amplitudes. The quench started at 10 A and was completed within 1 msec at the fault current of 65 A$_{peak}$. The dynamic quench characteristics were explained based on the heat conduction within the film and the heat transfer between the film and the surrounding liquid nitrogen. The heat transfer coefficient per unit area was estimated to be 3.0 W/cm$^2$K.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.806-809
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• 2003

Ion-induced secondary electron emission coefficient $({\gamma})$. of the patterned MgO thin film with geometrical structures has been measured by ${\gamma}$ - FIB(focused ion beam) system. The patterned MgO thin film with geometrical structures has been formed by the mask (mesh of ${\sim}$ $10{\mu}m^{2})$ under electron beam evaporation method. It is found that the higher ${\gamma}$. has been achieved by the patterned MgO thin film than the normal ones without patterning.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.390-390
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• 2010

We fabricate Schottky diodes with the contact between a sol-gel derived ZnO layer and Au that guarantees the expected Schottky contact due to the high work function. The formed single metal Schottky barrier shows characteristics comparable to the barrier formed by alloys. Au is deposited by thermal evaporation on a ZnO thin film that is optimally formed under sol-gel process conditions of a 1-mol zinc acetate concentration and a 3000-rpm coating speed. Possible defects. which can provide deleterious current paths. are minimized by patterning the deposited Au. The I-V curve verifies the formation of a Schottky contact. Measurements showed that the Schottky barrier height and leakage current at -5 V were 0.6 eV and $1{\times}10^{-12}A$. respectively.