• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.132-132
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• 2010

In the nano-scale Si processing, patterning processes based on multilevel resist structures becoming more critical due to continuously decreasing resist thickness and feature size. In particular, highly selective etching of the first dielectric layer with resist patterns are great importance. In this work, process window for the infinitely high etch selectivity of silicon oxynitride (SiON) layers and silicon nitride (Si3N4) with EUV resist was investigated during etching of SiON/EUV resist and Si3N4/EUV resist in a CH2F2/N2/Ar dual-frequency superimposed capacitive coupled plasma (DFS-CCP) by varying the process parameters, such as the CH2F2 and N2 flow ratio and low-frequency source power (PLF). It was found that the CH2F2/N2 flow ratio was found to play a critical role in determining the process window for ultra high etch selectivity, due to the differences in change of the degree of polymerization on SiON, Si3N4, and EUV resist. Control of N2 flow ratio gave the possibility of obtaining the ultra high etch selectivity by keeping the steady-state hydrofluorocarbon layer thickness thin on the SiON and Si3N4 surface due to effective formation of HCN etch by-products and, in turn, in continuous SiON and Si3N4 etching, while the hydrofluorocarbon layer is deposited on the EUV resist surface.

• Transactions on Electrical and Electronic Materials
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• 제12권4호
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• pp.131-134
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• 2011

Back-end-of-line using ultra low-k (ULK; k < 2.5) has been required to reduce resistive capacitance beyond 45 nmtechnologies, because micro-processing units need higher speed and density. There are two strategies to manufacture ULK inter-layer dielectric (ILD) materials using an air-gap (k = 1). The former ULK and calcinations of ILD degrade the mechanical strength and induce a high cost due to the complication of following process, such as chemical mechanical polishing and deposition of the barrier metal. In contrast, the air-gap based low-k ILD with a relatively higher density has been researched on the trench-type with activity, but it has limited application to high density devices due to its high air-gap into the next metal layer. The height of air-gap into the next metal layer was reduced by changing to the via-typed air-gap, up to about 50% compared to that of the trench-typed air-gap. The controllable ULK was easily fabricated using the via-typed air-gap. It is thought that the via-type air-gap made the better design margin like via-patterning in the area with the dense and narrow lines.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.20-23
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• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing(CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical polishing(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commercial slurries pads, and post-CMP cleaning alternatives are discuss, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper deposition is a mature process from a historical point of view, but a very young process from a CMP perspective. While copper electro deposition has been used and studied for decades, its application to Cu damascene wafer processing is only now gaining complete acceptance in the semiconductor industry. The polishing mechanism of Cu-CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper passivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.

• 한국정밀공학회지
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• 제21권6호
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• pp.153-159
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• 2004

In this study, a new process to pattern directly on a thin metal layer using improved nano replication printing (nRP) process is suggested to evaluate the possibilities of fabricating a stamp for nano-imprinting. In the nRP process, any figure can be replicated from a bitmap figure file in the range of several micrometers with nano-scaled details. In the process, liquid-state resins are polymerized by two-photon absorption which is induced by femto-second laser. A thin gold layer was sputtered on a glass plate and then, designed patterns or figures were developed on the gold layer by newly developed top-down building approach. Generally, stamps fur nano-imprinting have been fabricated by using the costly electron-beam lithography process combined with a reactive ion-etching process. Through this study, the effectiveness of the improved nRP process is evaluated to make a stamp with the resolution of around 200nm with reduced cost.

• 한국전기전자재료학회논문지
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• 제18권3호
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• pp.231-236
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• 2005

To investigate the electrical properties at the single grainboundary of ZnO varistors, micro-electrodes were fabricated on the surface which was polished and thermally etched. Our micro-electrode had 2000 $\AA$ silicon nitride layer between micro-electrode and ZnO surface. This layer was deposited by PECVD and etched by RIE after photoresistor pattering process using by mask 1. The metal patterning of micro-electrodes used lift-off method. We found that the breakdown voltage of single grainboundary is about 3.5∼4.2 V at 0.1 mA on I-V curves. Also, capacitance-voltage measurement at single grainboundary gave several parameters( $N_{d}$, $N_{t}$, $\Phi$$_{b}$, t) which were related with grainboundary.ary.

• 한국결정성장학회:학술대회논문집
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• 한국결정성장학회 1996년도 The 9th KACG Technical Annual Meeting and the 3rd Korea-Japan EMGS (Electronic Materials Growth Symposium)
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• pp.494-496
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• 1996

The purpose of this study is to investigate the effect of process conditions on pore distribution in porous silicon layer prepared by electrochemical reaction. Porous silicon layers formed on p-type silicon wafer show the network structure of fine porse whose diameters are less than 100${\AA}$. In n-type porous silicon, selective growth was found on the pore surface by wet etching process after PR patterning. And numerical method showed high current density on the pore tip. With this result we confirmed that pore formation has two steps. First step is the initial attack on the surface and second step is the directional growth on the pore tip.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2000년도 High Temperature Superconductivity Vol.X
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• pp.252-256
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• 2000

We investigated resistance development in Au/YBCO thin film meander lines during quench. The meander lines were fabricated by coating YBCO films insitu with a gold layer and patterning them by photolithography. The center stripe quenched fastest even though the flux flow resistance that appeared upon the current passing the critical current was uniform. Quench started at an area of the center stripe and propagate both through the gold layer and the sapphire substrate. Quench propagation speed was uniform and 60 cm/s at 30 V$_{rms}$.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.574-574
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• 2012

We report a simple way of fabricating high-quality carbon nanoscrolls (CNSs) by taking advantage of strain relief due to large difference in strain at the interface of graphene and underlying layer. This method allows strain-controlled self rolling-up of monolayer graphene during etching process at predefined positions on SiO2/Si substrates by photolithography. The size and the length of the CNSs can be easily controlled by adjusting the thickness of the underlying layer and by pre-patterning. Raman spectroscopy studies show that the CNSs is free of significant defects, and the electronic structure and phonon dispersion are slightly different from those of two-dimensional graphene. The preparation of high-quality CNSs may open up new opportunities for both fundamental and applied research of CNSs.

• Journal of Information Display
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• 제8권2호
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• pp.5-9
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• 2007

We demonstrate novel soft-lithographic techniques for preparing patterned liquid crystal (LC) orientations at an alignment layer. By controlling patterning conditions such as wetting property and operating temperature depending on polymeric materials, multi-directional or modified LC alignment conditions can be simply achieved.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2004년도 춘계학술대회
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• pp.1364-1369
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• 2004

New method for the design, fabrication, and calibration of micro-machined heat flux sensor has been developed. Two types of micro-machined heat flux sensor having different thicknesses of the thermal-resistance layer are fabricated using the MEMS technique. Photo-resist patterning using a chrome mask, bulk-etching and copper-nickel sputtering using a shadow mask are applied to make heat flux sensors, which are calibrated in the convection-type heat flux calibration facility. The sensitivity of the device varies with thermal-resistance layer, and hence can be used to measure the heat flux in heat-transfer phenomena.