• 제목/요약/키워드: Parylene layer

검색결과 38건 처리시간 0.024초

종이위에 구현한 유기박막트랜지스터의 특성 (Polymer Thin Film Transistors Fabricated on Photo Paper)

  • 성재용;김영훈;문대규;한정인;곽성관;정관수
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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    • pp.489-492
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    • 2004
  • In this paper, we demonstrate polymer thin-film transistors (TFTs) on a paper-based flexible substrate. As a substrate, commercially available photo-paper is used with Parylene coating. The parylene layer enables conventionally used wet chemical process and vacuum deposition processes for electrodes and gate insulator. As an active channel layer, we used poly-3-hexylthiophene (P3HT) which is solution process. Field effect mobility up to $(0.06 {\pm} 0.02) cm^2/Vs$ and on/off ratio of $10^3 {\~}10^4$ are achieved on a photo-paper.

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종이 기판을 이용한 유기박막 트랜지스터의 제작 (Polymer Thin-Film Transistors Fabricated on a Paper)

  • 김영훈;문대규;한정인
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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    • pp.504-505
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    • 2005
  • In this report, we demonstrate a high performance polymer thin-film transistor fabricated on a paper substrate. As a water barrier layer, parylene was coated on the paper substrate by using vacuum deposition process. Using poly (3-hexylthiophene) as an active layer, a polymer thin-film transistor with field-effect of up to 0.086 $cm^2/V{\cdot}s$ and on/off ratio of $10^4$ was achieved. The fabrication of polymer thin-film transistor built on a cheap paper substrate is expected to open a channel for future applications in flexible and disposable electronics with extremely low-cost.

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Threshold Voltage control of Pentacene Thin-Film Transistor with Dual-Gate Structure

  • Koo, Jae-Bon;Ku, Chan-Hoe;Lim, Sang-Chul;Lee, Jung-Hun;Kim, Seong-Hyun;Lim, Jung-Wook;Yun, Sun-Jin;Yang, Yong-Suk;Suh, Kyung-Soo
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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    • pp.1103-1106
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    • 2006
  • We have presented a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_2O_3$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_2O_3$ as both a top gate dielectric and a passivation layer is reported. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric is changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_2O_3$ as a top gate dielectric is changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode is changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure has been successfully understood by an analysis of electrostatic potential.

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Threshold Voltage Control of Pentacene Thin-Film Transistor with Dual-Gate Structure

  • Koo, Jae-Bon;Ku, Chan-Hoe;Lim, Sang-Chul;Lee, Jung-Hun;Kim, Seong-Hyun;Lim, Jung-Wook;Yun, Sun-Jin;Yang, Yong-Suk;Suh, Kyung-Soo
    • Journal of Information Display
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    • 제7권3호
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    • pp.27-30
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    • 2006
  • This paper presents a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_{2}O_{3}$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_{2}O_{3}$ as both a top gate dielectric and a passivation layer was investigated. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric was changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_{2}O_{3}$ as a top gate dielectric was changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode was changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure was successfully investigated by an analysis of electrostatic potential.

A Polycrystalline CdZnTe Film and Its X-ray Response Characteristics for Digital Radiography

  • Kim, Jae-Hyung;Park, Chang-Hee;Kang, Sang-Sik;Nam, Sang-Hee
    • Transactions on Electrical and Electronic Materials
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    • 제4권5호
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    • pp.15-18
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    • 2003
  • The Cd$\_$1-x/Zn$\_$x/Te film was produced by thermal evaporation for the flat-panel X-ray detector. The crystal structure and the surface morphology of poly crystalline Cd$\_$1-x/Zn$\_$x/Te film were examined using XRD and SEM, respectively. The leakage current and X-ray sensitivity of the fabricated films were measured to analyze the X-ray response characteristic of Zn in a polycrystalline CdZnTe thin film. The leakage current and the output charge density of Cd$\_$0.7/Zn$\_$0.3/Te thin film were measured to 0.3 1nA/$\textrm{cm}^2$ and 260 pC/$\textrm{cm}^2$ at an applied voltage of 2.5 V/$\mu\textrm{m}$, respectively. Experimental results showed that the increase of Zn doping rates in Cd$\_$1-x/Zn$\_$x/Te detectors reduced the leakage current and improved the X-ray sensitivity significantly. The leakage current was drastically diminished by the formation of thin parylene layer in the Cd$\_$0.7/Zn$\_$0.3/Te detector.

고속시스템을 위한 새로운 단일칩 패키지 구조 (A Novel Chip Scale Package Structure for High-Speed systems)

  • 권기영;김진호;김성중;권오경
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2001년도 추계 기술심포지움
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    • pp.119-123
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    • 2001
  • In this paper, a new structure and fabrication method for the wafer level package(WLP) is presented. A packaged VLSI chip is encapsulated by a parylene(which is a low k material) layer as a dielectric layer and is molded by SUB photo-epoxy with dielectric constant of 3.0 at 100 MHz. The electrical parameters (R, L, C) of package traces are extracted by using the Maxwell 3-D simulator. Based on HSPICE simulation results, the proposed wafer level package can operate for frequencies up to 20GHz.

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미세접촉프린팅 공정을 이용한 유연성 유기박막소자(OTFT)설계 및 제작 (Design and Fabrication of Flexible OTFTs by using Nanocantact Printing Process)

  • 조정대;김광영;이응숙;최병오
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2005년도 추계학술대회 논문집
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    • pp.506-508
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    • 2005
  • In general, organic TFTs are comprised of four components: gate electrode, gate dielectric, organic active semiconductor layer, and source and drain contacts. The TFT current, in turn, is typically determined by channel length and width, carrier field effect mobility, gate dielectric thickness and permittivity, contact resistance, and biasing conditions. More recently, a number of techniques and processes have been introduced to the fabrication of OTFT circuits and displays that aim specifically at reduced fabrication cost. These include microcontact printing for the patterning of metals and dielectrics, the use of photochemically patterned insulating and conducting films, and inkjet printing for the selective deposition of contacts and interconnect pattern. In the fabrication of organic TFTs, microcontact printing has been used to pattern gate electrodes, gate dielectrics, and source and drain contacts with sufficient yield to allow the fabrication of transistors. We were fabricated a pentacene OTFTs on flexible PEN film. Au/Cr was used for the gate electrode, parylene-c was deposited as the gate dielectric, and Au/Cr was chosen for the source and drain contacts; were all deposited by ion-beam sputtering and patterned by microcontact printing and lift-off process. Prior to the deposition of the organic active layer, the gate dielectric surface was treated with octadecyltrichlorosilane(OTS) from the vapor phase. To complete the device, pentacene was deposited by thermal evaporation and patterned using a parylene-c layer. The device was shown that the carrier field effect mobility, the threshold voltage, the subthreshold slope, and the on/off current ratio were improved.

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Free Floating 구조를 갖는 마이크로 밸브의 제작 (A Fabrication of the Micro Valve with Free Floating Structure)

  • 손미영;문병필;전호승;한진우;김철주
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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    • pp.136-139
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    • 2002
  • Previous valves have initial gap problem, high voltage or high pressure problem. In this paper, various micro valves with free floating structure have been fabricated and tested to solve the initial gap and high pressure problems. The paper presents how to etch Parylene-C which is a valve cap material without A1 mask layer. The maximum flow-rate of fabricated micro valve is$118{\mu\ell}$/min with $370{\mu}m$ orifice size and the leakage at the initial and reverse pressure is not observed.

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X-ray Sensitivity of Hybrid-type Sensor based on CaWO4-Selenium for Digital X-ray Imager

  • Park, Ji-Koon;Park, Jang-Yong;Kang, Sang-Sik;Lee, Dong-Gil;Kim, Jae-Hyung;Nam, Sang-Hee
    • Transactions on Electrical and Electronic Materials
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    • 제5권4호
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    • pp.133-137
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    • 2004
  • The development of digital x-ray detector has been extensively progressed for the application of various medical modalities. In this study, we introduce a new hybrid-type x-ray detector to improve problems of a conventional direct or indirect digital x-ray image technology, which composed of multi-layer structure using a CaWO$_4$ phosphor and amorphous selenium (a-Se) photoconductor. The leakage current of our detector was found to be ∼180 pA/cm$^2$ at 10 V/m, which was significantly reduced than that of a single a-Se detector. The x-ray sensitivity was measured as the value of 4230 pC/cm$^2$/mR at 10 V/m. We found that the parylene thin film between a CaWO$_4$ phosphor and an a-Se layer acts as an insulator to prevent charge injection from indium thin oxide (ITO) electrode into an a-Se layer under applied bias.

혼합형 X선 센서에서 a-Se 의 Iodine 첨가비 연구 (The Study on Composition ratio of Iodine in Hybrid X-ray Sensor)

  • 공현기;박지군;최장용;문치웅;남상희
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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    • pp.366-369
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    • 2002
  • At present, the study of direct digital X-ray detector and indirect digital X-ray detector proceed actively. But it needs high thickness and high voltage in selenium for high ionization rate. Therefore, we carried out the study of electric characteristics of a-Se with additive ratio of Iodine in drafting study for developing Hybrid X -ray Sensor for complementing direct digital X -ray detector and indirect digital X-ray detector in this paper. On this, there are formed Amorphous selenium multi-layers by sticking phosphor layer$(Gd_{2}O_{2}S(Eu^{2+}))$ using optical adhesives of EFIRON Co. Amorphous selenium multi-layers having dielectric layer(parylene) has characteristics of low dark-current, high X-ray sensitivity. So we can acquired a enhanced signal to noise ratio. We make Amorphous selenium multi-layers with $30{\mu}m$ thickness on glass.

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