• Title/Summary/Keyword: Partitioning Technique

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Understory Evapotranspiration Measured by Eddy-Covariance in Gwangneung Deciduous and Coniferous Forests (광릉 활엽수림과 침엽수림에서 에디공분산으로 관측한 하부 군락의 증발산)

  • Kang, Min-Seok;Kwon, Hyo-Jung;Lim, Jong-Hwan;Kim, Joon
    • Korean Journal of Agricultural and Forest Meteorology
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    • v.11 no.4
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    • pp.233-246
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    • 2009
  • The partitioning of evapotranspiration (ET) into evaporation (E) and transpiration (T) is critical in understanding the water cycle and the couplings between the cycles of energy, water, and carbon. In forests, the total ET measured above the canopy consists of T from both overstory and understory vegetation, and E from soil and the intercepted precipitation. To quantify their relative contributions, we have measured ET from the floors of deciduous and coniferous forests in Gwangneung using eddy covariance technique from 1 June 2008 to 31 May 2009. Due to smaller eddies that contribute to turbulent transfer near the ground, we performed a spectrum analysis and found that the errors associated with sensor separation were <10%. The annual sum of the understory ET was 59 mm (16% of total ET) in the deciduous forest and 43 mm (~7%) in the coniferous forest. Overall, the understory ET was not negligible except during the summer season when the plant area index was near its maximum. In both forest canopies, the decoupling factor ($\Omega$) was about ~0.15, indicating that the understory ET was controlled mainly by vapor pressure deficit and soil moisture content. The differences in the understory ET between the two forest canopies were due to different environmental conditions within the canopies, particularly the contrasting air humidity and soil water content. The non-negligible understory ET in the Gwangneung forests suggests that the dual source or multi-level models are required for the interpretation and modeling of surface exchange of mass and energy in these forests.

Model-Based Plane Detection in Disparity Space Using Surface Partitioning (표면분할을 이용한 시차공간상에서의 모델 기반 평면검출)

  • Ha, Hong-joon;Lee, Chang-hun
    • KIPS Transactions on Software and Data Engineering
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    • v.4 no.10
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    • pp.465-472
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    • 2015
  • We propose a novel plane detection in disparity space and evaluate its performance. Our method simplifies and makes scenes in disparity space easily dealt with by approximating various surfaces as planes. Moreover, the approximated planes can be represented in the same size as in the real world, and can be employed for obstacle detection and camera pose estimation. Using a stereo matching technique, our method first creates a disparity image which consists of binocular disparity values at xy-coordinates in the image. Slants of disparity values are estimated by exploiting a line simplification algorithm which allows our method to reflect global changes against x or y axis. According to pairs of x and y slants, we label the disparity image. 4-connected disparities with the same label are grouped, on which least squared model estimates plane parameters. N plane models with the largest group of disparity values which satisfy their plane parameters are chosen. We quantitatively and qualitatively evaluate our plane detection. The result shows 97.9%와 86.6% of quality in our experiment respectively on cones and cylinders. Proposed method excellently extracts planes from Middlebury and KITTI dataset which are typically used for evaluation of stereo matching algorithms.

An Efficient Dual Queue Strategy for Improving Storage System Response Times (저장시스템의 응답 시간 개선을 위한 효율적인 이중 큐 전략)

  • Hyun-Seob Lee
    • Journal of Internet of Things and Convergence
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    • v.10 no.3
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    • pp.19-24
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    • 2024
  • Recent advances in large-scale data processing technologies such as big data, cloud computing, and artificial intelligence have increased the demand for high-performance storage devices in data centers and enterprise environments. In particular, the fast data response speed of storage devices is a key factor that determines the overall system performance. Solid state drives (SSDs) based on the Non-Volatile Memory Express (NVMe) interface are gaining traction, but new bottlenecks are emerging in the process of handling large data input and output requests from multiple hosts simultaneously. SSDs typically process host requests by sequentially stacking them in an internal queue. When long transfer length requests are processed first, shorter requests wait longer, increasing the average response time. To solve this problem, data transfer timeout and data partitioning methods have been proposed, but they do not provide a fundamental solution. In this paper, we propose a dual queue based scheduling scheme (DQBS), which manages the data transfer order based on the request order in one queue and the transfer length in the other queue. Then, the request time and transmission length are comprehensively considered to determine the efficient data transmission order. This enables the balanced processing of long and short requests, thus reducing the overall average response time. The simulation results show that the proposed method outperforms the existing sequential processing method. This study presents a scheduling technique that maximizes data transfer efficiency in a high-performance SSD environment, which is expected to contribute to the development of next-generation high-performance storage systems

A Lower Bound Estimation on the Number of Micro-Registers in Time-Multiplexed FPGA Synthesis (시분할 FPGA 합성에서 마이크로 레지스터 개수에 대한 하한 추정 기법)

  • 엄성용
    • Journal of KIISE:Computer Systems and Theory
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    • v.30 no.9
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    • pp.512-522
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    • 2003
  • For a time-multiplexed FPGA, a circuit is partitioned into several subcircuits, so that they temporally share the same physical FPGA device by hardware reconfiguration. In these architectures, all the hardware reconfiguration information called contexts are generated and downloaded into the chip, and then the pre-scheduled context switches occur properly and timely. Typically, the size of the chip required to implement the circuit depends on both the maximum number of the LUT blocks required to implement the function of each subcircuit and the maximum number of micro-registers to store results over context switches in the same time. Therefore, many partitioning or synthesis methods try to minimize these two factors. In this paper, we present a new estimation technique to find the lower bound on the number of micro-registers which can be obtained by any synthesis methods, respectively, without performing any actual synthesis and/or design space exploration. The lower bound estimation is very important in sense that it greatly helps to evaluate the results of the previous work and even the future work. If the estimated lower bound exactly matches the actual number in the actual design result, we can say that the result is guaranteed to be optimal. In contrast, if they do not match, the following two cases are expected: we might estimate a better (more exact) lower bound or we find a new synthesis result better than those of the previous work. Our experimental results show that there are some differences between the numbers of micro-registers and our estimated lower bounds. One reason for these differences seems that our estimation tries to estimate the result with the minimum micro-registers among all the possible candidates, regardless of usage of other resources such as LUTs, while the previous work takes into account both LUTs and micro-registers. In addition, it implies that our method may have some limitation on exact estimation due to the complexity of the problem itself in sense that it is much more complicated than LUT estimation and thus needs more improvement, and/or there may exist some other synthesis results better than those of the previous work.