• Journal of electromagnetic engineering and science
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• v.11 no.1
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• pp.62-69
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• 2011

This paper proposes a novel electrical characterization approach for a high-performance package system using an improved Partial Element Equivalent Circuit (PEEC). As the effect of interconnects becomes a pivotal factor for the performance of high-speed electronic systems, there is a great demand for an accurate equivalent model for interconnects. In particular, an equivalent model of interconnects is established in this paper for the Fine-Pitch Ball Grid Array (FBGA) package using the improved PEEC method. Based on the equivalent model, electrical characteristics are analyzed; furthermore, these are verified through the measurement results of a Vector Network Analyzer (VNA).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.5
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• pp.404-408
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• 2003

The characterization for several multi-layer embedded inductors with different structures was investigated. The optimized equivalent circuit models for several test structures were obtained from HSPICE. Building blocks are modeled using Partial element equivalent circuit method. The mean and the standard deviation of model parameters were extracted and predictive modeling was performed on different test structure. From this study, the characteristic of multi-layer inductors can be predicted.

• ETRI Journal
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• v.28 no.2
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• pp.182-190
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• 2006

The circuit modeling of interdigitated capacitors fabricated by high-k low-temperature co-fired ceramic (LTCC) sheets was investigated. The s-parameters of each test structure were measured from 50 MHz to 10 GHz, and the modeling was performed using these measured sparameters up to the first resonant frequency. Each test structure was divided into appropriate building blocks. The equivalent circuit of each building block was composed based on the partial element equivalent circuit (PEEC) method. Modeling was executed to optimize the parameters in the equivalent circuit of each building block. The validity of the extracted parameters was verified by the predictive modeling for the test structures with different geometry. After that, Monte Carlo analysis and sensitivity analysis were performed based on the extracted parameters. The modeling methodology can allow a device designer to improve the yield and to save time and cost for the design and manufacturing of devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.130-133
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• 2004

The characterization of interdigitated capacitors was investigated. The test structures are manufactured by low temperature co-fired ceramic(LTCC) process and their s-parameters were measured. The optimized equivalent circuit models for test structures were obtained using the partial element equivalent circuit(PEEC) method. Predictive modeling was performed on different test structures using optimized parameters to verify the circuit models. From this result, the manufacturability on the process can be improved through the predictive modeling for the characteristics of interdigitated capacitors.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.57-58
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• 2005

The properties such as capacitance and resonant frequency are important in embedded capacitors. Accurate equivalent model is required to find these properties of embedded capacitor. In this paper, we investigate to analyze the properties of high-K embedded capacitor which was fabricated by Low Temperature Co-fired Ceramic (LTCC). Modeling based on partial element equivalent circuit (PEEC) method is performed using HSPICE circuit simulation. This modeling methodology can provide the good inspection of embedded capacitor to device engineer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.669-672
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• 2003

With the advances on wireless internet technology, many research on minimization of wireless LAN is on the progress. To apply passive components in MCM, characteristic analysis of passive components is essential. In this paper, three square spiral inductors were modeled by HSPICE using PEEC (Partial Element Equivalent Circuit) method. Afterwards, Monte-Carlo analysis was performed to evaluate the optimized parameters. This work will give an idea on PEEC modeling of spiral inductor, and enable researchers with predictive data before large scale manufacturing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.23-32
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• 2006

Fast and accurate power bus design (FAPUD) method for multi-layers high-speed digital boards is devised for the power supply network design tool for accurate and precise high speed board. FAPUD is constructed, based on two main algorithms of the PBEC (Path Based Equivalent Circuit) model and the network synthesis method. The PBEC model exploits simple arithmetic expressions of the lumped 1-D circuit model from the electrical parameters of a 2-D power distribution network. The circuit level design based on PBEC is carried with the proposed regional approach. The circuit level design directly calculates and determines the size of on-chip decoupling capacitors, the size and the location of off-chip decoupling capacitors, and the effective inductances of the package power bus. As a design output, a lumped circuit model and a pre-layout of the power bus including a whole decoupling capacitors are obtained after processing FAPUD. In the tuning procedure, the board re-optimization considering simultaneous switching noise (SSN) added by I/O switching can be carried out because the I/O switching effect on a power supply noise can be estimated over the operation frequency range with the lumped circuit model. Furthermore, if a design changes or needs to be tuned, FAPUD can modify design by replacing decoupling capacitors without consuming other design resources. Finally, FAPUD is accurate compared with conventional PEEC-based design tools, and its design time is 10 times faster than that of conventional PEEC-based design tools.

• ETRI Journal
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• v.28 no.3
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• pp.347-354
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• 2006

The characteristic variation of 3-dimensional (3-D) solenoid-type embedded inductors is investigated. Four different structures of a 3-D inductor are fabricated by using a low-temperature co-fired ceramic (LTCC) process, and their s-parameters are measured between 50 MHz and 5 GHz. The circuit model parameters of each building block are optimized and extracted using the partial element equivalent circuit method and an HSPICE circuit simulator. Based on the model parameters, the characteristics of the test structures such as self-resonant frequency, inductance, and quality (Q) factor are analyzed, and predictive modeling is applied to the structures composed of a combination of the modeled building blocks. In addition, characteristic variations of the 3-D inductors with different structures using extracted building blocks are also investigated. This approach can provide a characteristic estimation of 3-D solenoid embedded inductors for structural variations.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.38-39
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• 2006

In this paper, we describe a method of accurate modeling capacitor in Low Temperature Co-fired Ceramic(LTCC). We obtain building blocks that present characterization of test structure through partial element equivalent circuit (PEEC) method. The extracted model of building blocks can be used for predicting behaviors of capacitors with different geometries. This method can provide the good inspection of capacitor to device engineer.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.9-15
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• 2006

This paper shows the impedance profile of PEEC(Partial Equivalent Electrical Circuit) PDN(Power Distribution Networks) including core and I/O circuit. Through the simulated results, we find that the core power noise having connection with I/O power is affected by I/O switching. Also, using designed $74{\times}5inch$ DLL(Delay Locked Loop) test board, we analyzed the effect of power noise on operation region of chip. Jitter of a DLL measure for frequency of $50{\sim}400MHz$ and compared with impedance obtained result of simulation. Jitter of a DLL are increased near about frequency of 100MHz. It is reason that the resonant peak of PDNs has an impedance of more the 1ohm on 100MHz. we present the impedance profile of a chip and board for the decoupling capacitor reduced the target impedance. Therefore, power supply network design should be considered not only decoupling capacitors but also core switching current and I/O switching current.