• 대한전자공학회논문지SD
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• 제39권1호
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• pp.67-75
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• 2002

본 논문에서는 대략적인 PEEC 방법에 대해 논의 하고, 도선에 대하여 PEEC 등가회로를 구성하였으며, 주어진 등가회로로 부터 시스템의 행렬을 구하고, 이 행렬을 수치 해석적인 방법을 이용한 시뮬레이션을 수행하여 노드에서의 전압과 전류를 구하였다. PEEC 등가 회로를 구성하기 위해서, PEEC 등가 회로를 구성하는 성분(R, L, C)을 유한 요소법(finite element method)을 이용한 시뮬레이터를 이용하여 추출하였으며, 생성된 등가 회로에 대한 과도 해석을 수행하였다.

• Journal of electromagnetic engineering and science
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• 제11권1호
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• pp.62-69
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• 2011

This paper proposes a novel electrical characterization approach for a high-performance package system using an improved Partial Element Equivalent Circuit (PEEC). As the effect of interconnects becomes a pivotal factor for the performance of high-speed electronic systems, there is a great demand for an accurate equivalent model for interconnects. In particular, an equivalent model of interconnects is established in this paper for the Fine-Pitch Ball Grid Array (FBGA) package using the improved PEEC method. Based on the equivalent model, electrical characteristics are analyzed; furthermore, these are verified through the measurement results of a Vector Network Analyzer (VNA).

• 한국전기전자재료학회논문지
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• 제16권5호
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• pp.404-408
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• 2003

The characterization for several multi-layer embedded inductors with different structures was investigated. The optimized equivalent circuit models for several test structures were obtained from HSPICE. Building blocks are modeled using Partial element equivalent circuit method. The mean and the standard deviation of model parameters were extracted and predictive modeling was performed on different test structure. From this study, the characteristic of multi-layer inductors can be predicted.

• ETRI Journal
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• 제28권2호
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• pp.182-190
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• 2006

The circuit modeling of interdigitated capacitors fabricated by high-k low-temperature co-fired ceramic (LTCC) sheets was investigated. The s-parameters of each test structure were measured from 50 MHz to 10 GHz, and the modeling was performed using these measured sparameters up to the first resonant frequency. Each test structure was divided into appropriate building blocks. The equivalent circuit of each building block was composed based on the partial element equivalent circuit (PEEC) method. Modeling was executed to optimize the parameters in the equivalent circuit of each building block. The validity of the extracted parameters was verified by the predictive modeling for the test structures with different geometry. After that, Monte Carlo analysis and sensitivity analysis were performed based on the extracted parameters. The modeling methodology can allow a device designer to improve the yield and to save time and cost for the design and manufacturing of devices.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.130-133
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• 2004

The characterization of interdigitated capacitors was investigated. The test structures are manufactured by low temperature co-fired ceramic(LTCC) process and their s-parameters were measured. The optimized equivalent circuit models for test structures were obtained using the partial element equivalent circuit(PEEC) method. Predictive modeling was performed on different test structures using optimized parameters to verify the circuit models. From this result, the manufacturability on the process can be improved through the predictive modeling for the characteristics of interdigitated capacitors.

• ETRI Journal
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• 제28권3호
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• pp.347-354
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• 2006

The characteristic variation of 3-dimensional (3-D) solenoid-type embedded inductors is investigated. Four different structures of a 3-D inductor are fabricated by using a low-temperature co-fired ceramic (LTCC) process, and their s-parameters are measured between 50 MHz and 5 GHz. The circuit model parameters of each building block are optimized and extracted using the partial element equivalent circuit method and an HSPICE circuit simulator. Based on the model parameters, the characteristics of the test structures such as self-resonant frequency, inductance, and quality (Q) factor are analyzed, and predictive modeling is applied to the structures composed of a combination of the modeled building blocks. In addition, characteristic variations of the 3-D inductors with different structures using extracted building blocks are also investigated. This approach can provide a characteristic estimation of 3-D solenoid embedded inductors for structural variations.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.57-58
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• 2005

The properties such as capacitance and resonant frequency are important in embedded capacitors. Accurate equivalent model is required to find these properties of embedded capacitor. In this paper, we investigate to analyze the properties of high-K embedded capacitor which was fabricated by Low Temperature Co-fired Ceramic (LTCC). Modeling based on partial element equivalent circuit (PEEC) method is performed using HSPICE circuit simulation. This modeling methodology can provide the good inspection of embedded capacitor to device engineer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.2
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• pp.669-672
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• 2003

With the advances on wireless internet technology, many research on minimization of wireless LAN is on the progress. To apply passive components in MCM, characteristic analysis of passive components is essential. In this paper, three square spiral inductors were modeled by HSPICE using PEEC (Partial Element Equivalent Circuit) method. Afterwards, Monte-Carlo analysis was performed to evaluate the optimized parameters. This work will give an idea on PEEC modeling of spiral inductor, and enable researchers with predictive data before large scale manufacturing.

• 한국전자파학회논문지
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• 제14권8호
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• pp.823-829
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• 2003

고주파용 마이크로스트립 선로의 모델링에 필수적인 인덕턴스의 빠른 추출을 위해서 고속화 알고리즘(fast mutilpole method)과 결합된 적응 PEEC 격자분할법(adaptive PEEC grid refinement algorithm)을 제안하였다. 격자의 세분화는 마이크로스트립 선로의 구조와 사용주파수에 따른 전류분포에 적합하도록 이루어졌는데, 이 적응 격자는 주로 전류분포가 높은 영역에서 더 세분화된다. 이 기법을 이용하여 마이크로스트립 선로의 인덕턴스를 구하였고, 계산결과는 빠르게 수렴하여 계산시간과 격자 수를 줄이는데 효율적임을 보였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.38-39
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• 2006

In this paper, we describe a method of accurate modeling capacitor in Low Temperature Co-fired Ceramic(LTCC). We obtain building blocks that present characterization of test structure through partial element equivalent circuit (PEEC) method. The extracted model of building blocks can be used for predicting behaviors of capacitors with different geometries. This method can provide the good inspection of capacitor to device engineer.