• Title/Summary/Keyword: Parity Bit

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A Low Density Parity Check Coding using the Weighted Bit-flipping Method (가중치가 부과된 Bit-flipping 기법을 이용한 LDPC 코딩)

  • Joh, Kyung-Hyun;Ra, Keuk-Hwan
    • 전자공학회논문지 IE
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    • v.43 no.4
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    • pp.115-121
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    • 2006
  • In this paper, we proposed about data error check and correction on channel transmission in the communication system. LDPC codes are used for minimizing channel errors by modeling AWGN Channel as a VDSL system. Because LDPC Codes use low density parity bit, mathematical complexity is low and relating processing time becomes shorten. Also the performance of LDPC code is better than that of turbo code in long code word on iterative decoding algorithm. This algorithm is better than conventional algorithms to correct errors, the proposed algorithm assigns weights for errors concerning parity bits. The proposed weighted Bit-flipping algorithm is better than the conventional Bit-flipping algorithm and we are recognized improve gain rate of 1 dB.

Fast LDPC Decoding using Bit Plane Correlation in Wyner-Ziv Video Coding (와이너 지브 비디오 압축에서의 비트 플레인 상관관계를 이용한 고속 LDPC 복호 방법)

  • Oh, Ryanggeun;Shim, Hiuk Jae;Jeon, Byeungwoo
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.4
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    • pp.160-172
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    • 2014
  • Although Wyner-Ziv (WZ) video coding proves useful for applications employing encoders having restricted computing resources, the WZ decoder has a problem of excessive decoding complexity. It is mainly due to its iterative LDPC channel decoding process which repeatedly requests incremental parity data after iterative channel decoding of parity data received at each request. In order to solve the complexity problem, we divide bit planes into two groups and estimate the minimum required number of parity requests separately for the two groups of bit planes using bit plane correlation. The WZ decoder executes the iterative decoding process only after receiving parity data corresponding to the estimated minimum number of parity requests. The proposed method saves about 71% of the computing time in the LDPC decoding process.

Generalization of Tanner′s Minimum Distance Bounds for LDPC Codes (LDPC 부호 적용을 위한 Tanner의 최소 거리 바운드의 일반화)

  • Shin Min Ho;Kim Joon Sung;Song Hong Yeop
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.10C
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    • pp.1363-1369
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    • 2004
  • LDPC(Low Density Parity Check) codes are described by bipartite graphs with bit nodes and parity-check nodes. Tanner derived minimum distance bounds of the regular LDPC code in terms of the eigenvalues of the associated adjacency matrix. In this paper we generalize the Tanner's results. We derive minimum distance bounds applicable to both regular and blockwise-irregular LDPC codes. The first bound considers the relation between bit nodes in a minimum-weight codeword, and the second one considers the connectivity between parity nodes adjacent to a minimum-weight codeword. The derived bounds make it possible to describe the distance property of the code in terms of the eigenvalues of the associated matrix.

Fast Decoding Method of Distributed Video Based on Modeling of Parity Bit Requests (패리티 비트 요구량 모델링에 의한 분산 비디오의 고속 복호화 기법)

  • Kim, Man-Jae;Kim, Jin-Soo
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.11
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    • pp.2465-2473
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    • 2012
  • Recently, as one of low complexity video encoding methods, DVC (Distributed Video Coding) scheme has been actively studied. Most of DVC schemes exploit feedback channel to achieve better coding performances, however, this causes these schemes to have high decoding delay. In order to overcome these, this paper proposes a new fast DVC decoding method using parity-bit request model, which can be obtained by using bit-error rate, sent by encoder with motion vector, which is transmitted through feedback channel by decoder after generating side information. Through several simulations, it is shown that the proposed method improves greatly the decoding speed, compared to the conventional schemes.

Diagnosis and Improvement of mode transition delay in Linux 9bit serial communications (리눅스 9비트 시리얼통신에서 모드전환 지연원인의 분석과 개선)

  • Jeong, Seungho;Kim, Sangmin;Ahn, Heejune
    • Journal of Korea Society of Industrial Information Systems
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    • v.20 no.6
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    • pp.21-27
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    • 2015
  • We analyze the problem that is occurring when using parity mode transformation required for 9 bit serial communication under Linux environment and propose the solution. The parity mode change is used for 9 bit serial communication in the Linux that by nature supports only 8 bit serial communication. delay (around OS tick) arises. Our analysis shows that the cause is minimum length of waiting time to transmit data remained in Tx FIFO buffers. A modified Linux serial driver proposed in this paper decreases the delay less than 1ms by using accurate time delaying. Despite various system communication interfaces, enormous existing standards and system have adopted RS-232 serial communication, and the part of them have communicated by 9bit serial.

An analysis of BER performance of LDPC decoder for WiMAX (WiMAX용 LDPC 복호기의 비트오율 성능 분석)

  • Kim, Hae-Ju;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2010.05a
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    • pp.771-774
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    • 2010
  • In this paper, BER performance of LDPC(Low-Density Parity-Check) decoder for WiMAX is analyzed, and optimal design conditions of LDPC decoder are derived. The min-sum LDPC decoding algorithm which is based on an approximation of LLR sum-product algorithm is modeled and simulated by Matlab, and it is analyzed that the effects of LLR approximation bit-width and maximum iteration cycles on the bit error rate(BER) performance of LDCP decoder. The parity check matrix for IEEE 802.16e standard which has block length of 2304 and code rate of 1/2 is used, and AWGN channel with QPSK modulation is assumed. The simulation results show that optimal BER performance is achieved for 7 iteration cycles and LLR bit-width of (8,6).

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Nonbinary Multiple Rate QC-LDPC Codes with Fixed Information or Block Bit Length

  • Liu, Lei;Zhou, Wuyang;Zhou, Shengli
    • Journal of Communications and Networks
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    • v.14 no.4
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    • pp.429-433
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    • 2012
  • In this paper, we consider nonbinary quasi-cyclic low-density parity-check (QC-LDPC) codes and propose a method to design multiple rate codes with either fixed information bit length or block bit length, tailored to different scenarios in wireless applications. We show that the proposed codes achieve good performance over a broad range of code rates.

An Effective Quality Estimation in Pixel-domain Distributed Video Coding (화소영역 분산비디오 부호화기법에서 효과적인 화질 예측방법)

  • Kim, Jin-soo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.10a
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    • pp.1024-1026
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    • 2013
  • DVC (Distributed Video Coding) techniques provides a basic theory for the implementation of low-power video encoder. Conventional methods decide the parity bit request at decoder side. These are effective in controlling the bit-rate, but, are not able to control the visual quality. Thus, this paper presents an effective method of estimating visual quality improved by correcting the virtual channel noise for the reconstructed frame. Through several experiments, it is shown that the proposed method are able to estimate effectively the decoded visual quality.

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Effects of LDPCA Frame Size for Parity Bit Estimation Methods in Fast Distributed Video Decoding Scheme (고속 분산 비디오 복호화 기법에서 패리티 비트 예측방식에 대한 LDPCA 프레임 크기 효과)

  • Kim, Man-Jae;Kim, Jin-Soo
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.8
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    • pp.1675-1685
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    • 2012
  • DVC (Distributed Video Coding) technique plays an essential role in providing low-complexity video encoder. But, in order to achieve the better rate-distortion performances, most DVC systems need feedback channel for parity bit control. This causes the DVC-based system to have high decoding latency and becomes as one of the most critical problems to overcome for a real implementation. In order to overcome this problem and to accelerate the commercialization of the DVC applications, this paper analyzes an effect of LDPCA frame size for adaptive LDPCA frame-based parity bit request estimations. First, this paper presents the LDPCA segmentation method in pixel-domain and explains the temporal-based bit request estimation method and the spatial-based bit request estimation method using the statistical characteristics between adjacent LDPCA frames. Through computer simulations, it is shown that the better performance and fast decoding is observed specially when the LDPCA frame size is 3168 in QCIF resolution.

All-optical Integrated Parity Generator and Checker Using an SOA-based Optical Tree Architecture

  • Nair, Nivedita;Kaur, Sanmukh;Goyal, Rakesh
    • Current Optics and Photonics
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    • v.2 no.5
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    • pp.400-406
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    • 2018
  • The Semiconductor Optical Amplifier (SOA)-based Mach-Zehnder interferometer is a major contributor in all-optical digital processing and optical computation. Optical tree architecture provides one of the new, alternative schemes for integrated all-optical arithmetic and logical operations. In this paper, we propose an all-optical 3-bit integrated parity generator and checker using SOA-MZI-based optical tree architecture. The proposed scheme, able to process input signals at a desired operating wavelength, has been characterized using RZ-modulated signals at 10 Gbps. The maximum extinction ratios achieved at the output of the parity generator and checker are 10 dB and 8 dB respectively.