• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.2
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• pp.1-9
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• 1997

For the reduction of parasitic inductance and matching of bonding wire in the package of microwave devices, we propose multiple bonding wires buried in a dielectric material of FR-4 composite. This structure is analyzed using the method of moments (MoM) and compared with the common bondwires and ribbon interconnections. The FR-4 composite is modelled by the cole-cole model which can consider the loss and the variation of the permittivity in a frequency. At 20 GHz, the parasitic reactance is reduced by 90%, 80%, 60% compared to those of a single bonding wire in air, double bonding wires in air and ribbon interconnection in air, respectively. Also, the new bondwire shows very good matching of 60.ohm characteristic impedance and has 15dB, 10dB, 5dB improvement of the return loss and 2.5dB, 0.7dB, 0.2dB improvement of the insertion loss compared to the common interconnections. This technique can minimize the parasitic effect of bondwires in microwave device packaging.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.466-469
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• 2004

In this paper, we improve the matching impedance of antennas by inserting parasitic slots on the ground plane of right-angle triangular slot antennas. The designed antennas characteristics are analyzed by using Finite Different Time Domain (FDTD) method, the specific design frequency is 10 GHz and match impedance is 50 ohms. Simulation results show that the efficient of return loss and radiation patterns are improved and enhance. In this case, the right-angle triangular slot antennas with parasitic slots have matching impedance better than antennas without parasitic slots.

• Journal of Power Electronics
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• v.16 no.1
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• pp.374-387
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• 2016

This paper derives an improved analytical model to estimate switching loss and analyze the effects of parasitic elements on the switching performance of SiC MOSFETs. The proposed analytical model considers the parasitic inductances, the nonlinearity of the junction capacitances and the nonlinearity of the trans-conductance. The turn-on process and the turn-off process are illustrated in detail, and equivalent circuits are derived and solved for each switching transition. The proposed analytical model is more accurate and matches better with experimental results than other analytical models. Note that switching losses calculated based on experiments are imprecise, because the energy of the junction capacitances is not properly disposed. Finally, the proposed analytical model is utilized to account for the effects of parasitic elements on the switching performance of a SiC MOSFET, and the circuit design rules for high frequency circuits are given.

• Proceedings of the KIEE Conference
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• 1999.11b
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• pp.64-66
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• 1999

High-speed motors using permanent magnet have various merits; high efficiency, high power density, and small size. While they have merits, we have to solve some problems. First of all, we have to reduce loss, cause of heat, to realize high speed operation. The loss be composed of copper loss, iron loss, and parasitic rotor loss. Iron loss and parasitic rotor loss is proportional to frequency, square of frequency, respectively.

• Journal of Power Electronics
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• v.19 no.2
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• pp.591-601
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• 2019

With the development of renewable energy, grid-connected inverter technology has become an important research area. When compared with traditional silicon IGBT power devices, the silicon carbide (SiC) MOSFET shows obvious advantages in terms of its high-power density, low power loss and high-efficiency power supply system. It is suggested that this technology is highly suitable for three-phase AC motors, renewable energy vehicles, aerospace and military power supplies, etc. This paper focuses on the SiC MOSFET behaviors that concern the parasitic component influence throughout the whole working process, which is based on a three-phase grid-connected inverter. A high-speed model of power switch devices is built and theoretically analyzed. Then the power loss is determined through experimental validation.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.433-434
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• 1988

Rectangular microstrip antenna with parasitic element is analyzed. Radiation admittance and equivalent circuit parameters between rectangular microstrip antenna and parasitic element are obtained by using equivalent ${\pi}$-network parameters of the slit in the wall of the parallel plate waveguide filled with homogeneous dielectric. The return loss is calculated and measured as a function of frequency with gap width 0.5mm between the patch and parasitic element. The experimental results are in fairly agreement with calculated values.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.5
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• pp.874-879
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• 2016

A wideband stacked patch antenna with parasitic elements, rectangular and triangle shaped patches, is proposed. Two different shaped parasitic elements are placed in the above of main rectangular microstrip patch antenna in order to achieve wide bandwidth for 860 MHz band. Coupling between the main patch and parasitic patches is realized by thick air gap. The gap and locations of parasitic patches are found to be the main factor of the wideband impedance matching. The proposed antenna is designed and fabricated on a ground plane with small size of $119mm{\times}109mm$ for application of compact transceivers. The fabricated antenna on an FR4 substrate shows that the minimum measured return loss is below -11.68dB at 824 MHz and an impedance band of 818~919 MHz(11.7%) at 10dB return loss level. The measured radiation patterns are similar to those of a conventional patch antenna with maximum gain of 2.11 dBi at 824 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.1
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• pp.7-13
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• 2007

In this paper, we have designed and fabricated a small size wide-band monopole antenna which can integrate the frequency of previous business mobile communication system by adding 4 PCS of post type parasitic element on top-loaded sleeve monopole antenna. We have observed the properties of return loss upon a parameter change of element, and we also examined radiation properties in the band of PCS, W-CDMA, WiBro, W-LAN and S-DMB in order to make sure the suggested antenna's wide-band properties. We have found that the proposed antenna has omni-direction in horizontal plane and figure eight-direction in vertical plane, and we could have good return loss($Return\;loss{\leq}-10\;dB$) and $1.14{\sim}3.66\;dBi$ gain in $1.67{\sim}3.55\;GHz$ of frequency range($B/W{\fallingdotsep}72%$).

• Journal of electromagnetic engineering and science
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• v.7 no.3
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• pp.116-121
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• 2007

Novel design of a wideband monopole antenna for DVB-H service is presented. The proposed antenna is designed based on a monopole antenna. It consists of folded monopole and parallel parasitic element. The folded segment of the folded monopole makes the antenna shorter. The length of the parasitic element obtains additional resonance frequencies. The gap distance between the folded monopole and the parasitic element is a key parameter to control impedance matching for wideband operation. The antenna has wide band performance, good impedance and radiation characteristics from 470 MHz to 870 MHz. The measured return loss for operating frequencies over DVB-H band is better than 10 dB. Good radiation patterns are also obtained. The measured results are compared with calculated results using Ansoft HFSS(High Frequency Structure Simulator).

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.4
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• pp.538-542
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• 2018

In order to generate a clock source with low cost and high performance in system on chip(SoC), a relaxation oscillator with stable output characteristics according to PVT(process, voltage and temperature) fluctuation require a low area and a low power. In this paper, we propose a solution to reduce the current loss caused by parasitic components in the conventional relaxation oscillator. Since the slew rate of the bias current and the capacitor are adjusted to be the same through the proposed solution, a relaxation oscillator with low area characteristics is designed for the same clock source frequency implementation. The proposed circuit is designed using the TSMC CMOS 0.18um process. The Simulation results show that the relaxation oscillator using the proposed solution can prevent the current loss of about $279{\mu}A$ and reduce the total chip area by 20.8% compared with the conventional oscillator in the clock source frequency of 96 MHz.