• The Transactions of the Korean Institute of Power Electronics
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• v.28 no.1
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• pp.39-47
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• 2023

This paper applies a structural technique with uniform parallel switch characteristics in gates and power loops to minimize the ringing and current imbalance that occurs when a general discrete package (TO-247)-based power semiconductor device is operated in parallel. Also, this propose a heat sink integrated switching module with heat sink design flexibility and high power density. The developed heat dissipation-integrated switching module verifies the symmetry of the parasitic inductance of the parallel switch through Q3D by ansys and the validity of the structural technique of the parallel switch using the LLC resonant converter experiment operating at a rated capacity of 7.5 kW.

• Journal of the Korean Society of Industry Convergence
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• v.26 no.6_1
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• pp.985-991
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• 2023

This study proposes a solution to the voltage drop in electric vehicle chargers, due to the parasitic resistance and inductance of power cables when the chargers are separated by large distances. A method using multi-level electric vehicle chargers that can output power in stages, without installing an additional energy supply source such as a reactive power compensator or an energy storage system, is proposed. The voltage drop over the power cables, to optimize the charging scheduling, is derived. The obtained voltage drop equation is used to formulate the constraints of the optimization process. To validate the effectiveness of the obtained results, an optimal charging scheduling is performed for each period in a case study based on the assumed charging demands of three connected chargers. From the calculations, the proposed method was found to generate an annual profit of $20,800 for a $12,500 increase in installation costs.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.8
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• pp.873-879
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• 2007

We have implemented a highly efficient 2.14-GHz class-F amplifier using Freescale 4-W peak envelope power(PEP) RF Si lateral diffusion metal-oxide-semiconductor field effect transistor(LDMOSFET). Because the control of the all harmonic contents is very difficult, we have managed only the $2^{nd}\;and\;3^{rd}$ harmonics to obtain the high efficiency with simple harmonic control circuit. In order to design the harmonic control circuit accurately, we extracted the bonding wire inductance and drain-source capacitance which are dominant parasitic and package effect components of the device. And then, we have fabricated the class-F amplifier. The measured drain and power-added efficiency are 65.1 % and 60,3 %, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.1
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• pp.20-26
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• 2016

This paper presents an X-band two-stage power amplifier using GaN-HEMT. Two-stage structure was adopted to take its high gain and simple inter-stage matching network. Based on a 3D EM simulation, the bond-wire inductance and the parasitic capacitance were predicted. By reducing bond-wire inductance, Q of the matching network is decreased and the bandwidth is improved. The implemented two-stage PA shows a power gain of more than 16 dB, saturated output power of more than 42.5 dBm, and a efficiency of more than 35 % in frequency range of 8.1~8.5 GHz with an operating voltage of 40 V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.95-101
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• 2008

We have used diversely the multilayer ceramic oscillator of the SMD(Surface Mounted Device) package technology that connects the crystal with the chip package. Such an oscillator occurs a stray inductance and a parasitic capacitance by the length and inner pattern. And it has been happened an amplitude attenuation and signal loss due to the reflection of power source and noise component. So we don't evaluate the precise performance of the oscillator for these factors. In this paper we have developed the Jig system to evaluate the performance of the oscillator. Through this system, we will expect an advanced performance of the oscillator and redesign an oscillator of the low jitter characteristics and low phase noise.

• Journal of Power Electronics
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• v.18 no.2
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• pp.375-382
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• 2018

A novel active controlled primary current cutting-off zero-voltage and zero-current switching (ZVZCS) PWM three-level dc-dc converter (TLC) is proposed in this paper. The proposed converter has some attractive advantages. The OFF voltage on the primary switches is only Vin/2 due to the series connected structure. The leading-leg switches can obtain zero-voltage switching (ZVS), and the lagging-leg switches can achieve zero-current switching (ZCS) in a wide load range. Two MOSFETs, referred to as cutting-off MOSFETs, with an ultra-low on-state resistance are used as active controlled primary current cutting-off components, and the added conduction loss can be neglected. The added MOSFETs are switched ON and OFF with ZCS that is irrelevant to the load current. Thus, the auxiliary switching loss can be significantly minimized. In addition, these MOSFETs are not series connected in the circuit loop of the dc input bus bar and the primary switches, which results in a low parasitic inductance. The operation principle and some relevant analyses are provided, and a 6-kW laboratory prototype is built to verify the proposed converter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.21-26
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• 2004

In this paper, a direct method is developed to extact RF equivalent circuit of a packaged BJT without optimization. First, parasitic components of plastic package are removed from measured S-parameters using open and short package patterns. Using package do-embedded S-parameters, a direct and simple method is proposed to extract bonding wire inductance and chip pad capacitance between package lead and chip pad. The small-signal model parameters of internal BJT are next determined by Z and Y-parameter formula derived from RF equivalent circuit. The modeled S-parameters of packaged BJT agree well with measured ones, verifying the accuracy of this new extraction method.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.11
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• pp.17-22
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• 2000

A novel and robust direct parameter extraction method for hybrid-p equivalent circuit model of HBT is proposed. A new expression that can accurately resolve the base internal resistance from the measured S-parameters is derived, and it is not sensitive to the values of parasitic access inductance values. Based on the expression, six analytical expressions for the other parameters is developed and these expressions for hybrid-p equivalent circuit modeling ensure robust, fast, and reliable parameter extraction.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.96-102
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• 2009

This paper deals with gate drive and power IC for high power devices(600V/200A and 1200V/150A). The proposed gate driver provides high gate driving capability (4 A source, 8 A sink), and over-current protected by means of power transistor desaturation detection. In addition, soft-shutdown function is added to reduce voltage overshoots due to parasitic inductance. This gate drive If is designed, fabricated, and tested using the Dongbu hitek 0.35um BCDMOS process.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.4 s.310
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• pp.45-52
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• 2006

In his paper, we have developed the SMD(surface mounted device) type PECL(positive emitter-coupled logic) VCXO of the $5{\times}7mm$ size for gratifying the requested specifications and the multilayer ceramic SMD(surface mounted device) package technology. The VCXO wired with the PECL(positive emitter coupled logic) package take place a stray inductance and a parasitic capacitance by the length and the inner pattern of the VCXO and the amplitude attenuation and signal loss due to the reflection of power source and the noise component. We have developed the Zig system to analyze the precise spectrum and evaluate the performance. The basic operating voltage is the 3.3 V and have the frequency range of 120MHz-180MHz. The Q factor is over 5K and it has the low jitter characteristics of 3.5 ps and low phase noise.